Abstract: An integrated circuit designed to control grain growth induced roughening in a conductive stack is disclosed herein. The conductive stack includes an interconnect metallization layer formed at a low diffusivity temperature of less than 200° C. The interconnect metallization layer includes aluminum doped with copper. The conductive stack further includes subsequent depositions and/or processing involving interconnect metallization layer to be carried out at the low diffusivity temperatures.

Abstract: A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.

Abstract: Multi-metallization level semiconductor devices are formed without degrading a low k dielectric gap fill material due to multiple pre-metallization degassing/outgassing heat treatments. Degradation of the low k material is substantially reduced or eliminated by employing time intervals for heat treatment which are not longer than the longest metal deposition step and temperatures below that which the dielectric material decomposes.

Abstract: A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.

Abstract: A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Abstract: A transmission electron microscopy (TEM) or scanning electron microscopy (SEM) sample preparation method includes the steps of depositing a metal layer on top of a substrate, depositing a silicon nitride passivation layer on top of the metal layer, and cutting the substrate and the metal and passivation layers to expose their cross-sections for examination by electron microscopy. As a result, a TEM/SEM sample having sharp, well-defined boundaries is produced.

Abstract: A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: Improved methods for manufacturing semiconductor devices incorporating barrier layers at metal/dielectric interfaces include the use of nitrogen-rich plasma, ion beam implantation and/or electromagnetic radiation to form regions of nitrided metal. The barrier layers decrease the diffusion of dopants such as fluorine, phosphorous and boron from the dielectric material into the metal, thereby decreasing the formation of metal salts. By decreasing the formation of metal salts, the barrier layers of this invention decrease the formation of voids and areas of delamination, and thereby decrease the loss of electrical reliability during manufacture and during use. Additional aspects of this invention include methods for monitoring the deposition of thin metal films using sheet resistance measurements, and further embodiments of this invention include methods for monitoring the surface texture of films that undergo phase transitions.

Abstract: A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: An improved damascene metal interconnect for use in a semiconductor integrated circuit. By using highly directional deposition of barrier and/or seed layers the texture of the damascene structure is improved. A first barrier metal layer is deposited in a standard deposition manner, and a second barrier metal is then applied in a highly directional manner. For example, tungsten, titanium and tantalum nitrides can be used as barrier metals. Copper or aluminum based metal is deposited over the second barrier metal, and is then polished by using a chemical mechanical polish. A passivation layer can then be deposited over the interconnect.

Abstract: A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

Abstract: A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.

Abstract: In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.

Abstract: Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that is part of a control gate structure within a non-volatile memory cell. Cracks within the tungsten silicide layer can affect the performance of the memory cell by increasing the resistance of the control gate configuration. The methods and arrangements prevent cracking of the tungsten silicide layer by minimizing the relative difference between temperatures associated with the deposition of the tungsten suicide layer and deposition of a subsequent overlying cap layer.

Abstract: A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.

Abstract: A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Abstract: An aluminum fill process for sub-0.25 .mu.m technology integrated circuits that has a reflow temperature less than 400.degree. C. that has low alloy resistivity and excellent electromigration characteristics. The aluminum allow is composed of Al-1% Ge-1% Cu.

Abstract: Thin films of tungsten silicide are deposited by CVD on conductive lines under conditions controlled to minimize development of tensile stresses upon subsequent thermal processing, thereby reducing cracking and delamination. Embodiments include reducing the deposition temperature and/or adjusting the gas flow ratio of reactants, such that the as deposited tungsten silicide film does not undergo a significant increase in densification and/or crystallinity upon subsequent deposition of a polycrystalline silicon capping layer.

Abstract: A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.