Patents by Inventor Gudbjorg H. Oskarsdottir
Gudbjorg H. Oskarsdottir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8193072Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: November 2, 2010Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Publication number: 20110059596Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: ApplicationFiled: November 2, 2010Publication date: March 10, 2011Inventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7897486Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: May 9, 2007Date of Patent: March 1, 2011Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7446360Abstract: According to one aspect of the invention, a polymer device and a method of constructing a polymer device are provided. The polymer device includes a first conductor, a second conductor, and a polymeric body between the first and second conductors. The polymeric body includes a polymer material and a phyllosilicate material.Type: GrantFiled: August 9, 2004Date of Patent: November 4, 2008Assignee: Intel CorporationInventors: James C. Matayabas, Jr., Gudbjorg H. Oskarsdottir
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Patent number: 7279362Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: March 31, 2005Date of Patent: October 9, 2007Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7205595Abstract: An embodiment of the invention reduces damage caused to a polymer ferroelectric layer in a polymer ferroelectric memory device by creating excess holes in the insulating metal nitride and/or metal oxide layers between the metal electrodes and polymer ferroelectric layer. The excess holes in the metal nitride and/or metal oxide trap electrons injected by the metal electrodes under AC bias that would otherwise damage the polymer ferroelectric layer.Type: GrantFiled: March 31, 2004Date of Patent: April 17, 2007Assignee: Intel CorporationInventors: Mukul P. Renavikar, Gudbjorg H. Oskarsdottir
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Patent number: 7179689Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.Type: GrantFiled: November 18, 2005Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: James C. Matayabas, Jr., Gudbjorg H. Oskarsdottir, Mitesh C. Patel
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Patent number: 7170188Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.Type: GrantFiled: June 30, 2004Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: James C. Matayabas, Jr., Gudbjorg H. Oskarsdottir, Mitesh C. Patel
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Patent number: 6974726Abstract: A silicon wafer has a plurality of integrated circuits terminated on a surface of the silicon wafer. The silicon wafer has a soluble protective coat on the surface of the silicon wafer. The coated silicon wafer may be processed by laser scribing. A solvent wash may be used to remove the soluble protective coat and debris from laser scribing. The coated silicon wafer may be saw cut after laser scribing. A flow of solvent may be provided during the saw cutting. The flow of solvent may be sufficient to remove at least a substantial portion of the soluble protective coat.Type: GrantFiled: December 30, 2003Date of Patent: December 13, 2005Assignee: Intel CorporationInventors: Ashay A. Dani, Gudbjorg H. Oskarsdottir, Chris Matayabas, Jr., Sujit Sharan, Chris L. Rumer, Beverly J. Canham