Patents by Inventor Guee Hwang Sim
Guee Hwang Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8318408Abstract: In a method of forming patterns of a semiconductor device, a semiconductor substrate defining photoresist patterns formed over a target etch layer is provided. An auxiliary layer is formed over the semiconductor substrate and the photoresist patterns. The auxiliary layer formed on a surface of the photoresist patterns is denatured into first auxiliary patterns. A photoresist film is formed over the semiconductor substrate, the first auxiliary patterns, and the auxiliary layer. The auxiliary layer formed below the photoresist film is denatured into a second auxiliary pattern. Here, the auxiliary layer remains only between the photoresist patterns. Etch mask patterns, including the photoresist patterns and the auxiliary layer, are formed by removing the photoresist film and the first and second auxiliary patterns.Type: GrantFiled: June 30, 2009Date of Patent: November 27, 2012Assignee: Hynix Semiconductor Inc.Inventors: Woo Yung Jung, Guee Hwang Sim
-
Patent number: 8221961Abstract: The present invention relates to a method of manufacturing semiconductor devices. According to the method, an etch target layer, a chemically amplified photoresist layer, and an Anti-Reflective Coating (ARC) layer are first sequentially formed over a semiconductor substrate. An exposure process is performed in order to form exposure portions in the photoresist layer. A thermal process is performed so that a decrosslinking reaction is generated in the ARC layer on the exposure portions. A development process is performed in order to form photoresist layer patterns and ARC layer patterns by removing the ARC layer at portions in which the decrosslinking reaction has occurred and the exposure portions. A silylation process is performed in order to form silylation patterns on sidewalls of each of the photoresist layer patterns. The ARC layer patterns and the photoresist layer patterns are removed. The etch target layer is patterned using the silylation patterns as an etch mask.Type: GrantFiled: December 30, 2008Date of Patent: July 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Guee Hwang Sim
-
Patent number: 7851135Abstract: The present invention relates to a method of forming an etching mask pattern from developed negative and positive photoresist layers. According to the present invention, a negative photoresist layer is formed over a substrate. Some regions of the negative photoresist layer are exposed, thereby generating hydrogen ions within the exposed negative photoresist regions. The negative photoresist layer is developed so that the exposed negative photoresist regions remain. A positive photoresist layer is formed over the substrate including the remaining negative photoresist regions. The substrate is baked so that hydrogen ions within the remaining negative photoresist regions are diffused into the positive photoresist layer at boundary portions adjacent to the remaining negative photoresist regions. The positive photoresist layer is developed to remove the positive photoresist portions into which the hydrogen ions are diffused.Type: GrantFiled: November 30, 2007Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventors: Woo Yung Jung, Guee Hwang Sim
-
Patent number: 7687403Abstract: A method of manufacturing a flash memory device includes providing a substrate having an insulating layer, a first mask layer over the insulating layer, a second mask layer over the first mask layer, a first photoresist pattern over the second mask layer, the first photoresist pattern having a first pitch. A material layer is provided over the first photoresist pattern. The material layer is etched to convert the material layer into a material layer pattern having a second pitch that is less than the first pitch. The second hard mask layer is etched using the material layer pattern to form a second hard mask layer pattern that extends along a first direction. A second photoresist pattern is etched, the second photoresist pattern defining a first region that is not exposed and a second region that is exposed, the second region extending along a second direction that is orthogonal to the first direction.Type: GrantFiled: June 29, 2007Date of Patent: March 30, 2010Assignee: Hynix SemiconductorInventors: Guee Hwang Sim, Woo Yung Jung
-
Publication number: 20100021849Abstract: In a method of forming patterns of a semiconductor device, a semiconductor substrate defining photoresist patterns formed over a target etch layer is provided. An auxiliary layer is formed over the semiconductor substrate and the photoresist patterns. The auxiliary layer formed on a surface of the photoresist patterns is denatured into first auxiliary patterns. A photoresist film is formed over the semiconductor substrate, the first auxiliary patterns, and the auxiliary layer. The auxiliary layer formed below the photoresist film is denatured into a second auxiliary pattern. Here, the auxiliary layer remains only between the photoresist patterns. Etch mask patterns, including the photoresist patterns and the auxiliary layer, are formed by removing the photoresist film and the first and second auxiliary patterns.Type: ApplicationFiled: June 30, 2009Publication date: January 28, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Woo Yung Jung, Guee Hwang Sim
-
Patent number: 7651933Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer and fill the first trench. A second trench is formed by patterning the pad layer and removing an exposed semiconductor substrate, the second trench being formed within the first trench. An ion implantation process is performed on the semiconductor substrate exposed through the second trench.Type: GrantFiled: December 5, 2007Date of Patent: January 26, 2010Assignee: Hynix Semiconductor Inc.Inventor: Guee-Hwang Sim
-
Patent number: 7638263Abstract: An overlay accuracy measurement vernier and a method of forming the same. According to one embodiment, the method of forming the overlay accuracy measurement vernier includes the steps of forming a first vernier pattern in a predetermined region on a semiconductor substrate; etching the semiconductor substrate using the first vernier pattern as a mask, forming a trench of a first depth; forming a second vernier pattern having a width wider than that of the first vernier pattern, the second vernier pattern including the first vernier pattern; performing an etch process using the second vernier pattern as a mask, thus forming a trench of a second depth, which has a step of a predetermined width; stripping the first and second vernier patterns and then forming an insulating film to bury the trench; and, etching the insulating film so that the semiconductor substrate of the vernier region is exposed.Type: GrantFiled: June 30, 2006Date of Patent: December 29, 2009Assignee: Hynix Semiconductor Inc.Inventor: Guee Hwang Sim
-
Patent number: 7595145Abstract: A method of forming a pattern of a semiconductor device includes forming a hard mask layer over a semiconductor substrate and forming a photoresist film pattern over the hard mask layer. An outer portion of the photoresist film pattern is converted into an oxide layer having a first vertical wall, a second vertical wall, and a horizontal wall, wherein an inner portion of the photoresist film pattern is enclosed within the converted oxide layer. At least a portion of the horizontal wall is removed to expose the photoresist film pattern remaining within the converted oxide layer. The exposed photoresist film pattern is removed to form first and second oxide patterns corresponding to the first and second vertical walls, respectively, of the oxide layer. The hard mask layer is patterned using the first and second oxide patterns as etch masks. The semiconductor substrate is etched using the patterned hard mask layer.Type: GrantFiled: December 21, 2006Date of Patent: September 29, 2009Assignee: Hynix Semiconductor Inc.Inventors: Guee Hwang Sim, Woo Yung Jung
-
Publication number: 20090181327Abstract: The present invention relates to a method of manufacturing semiconductor devices. According to the method, an etch target layer, a chemically amplified photoresist layer, and a Bottom Anti-Reflective Coating (BARC) layer are first sequentially formed over a semiconductor substrate. An exposure process is performed in order to form exposure portions in the photoresist layer. A thermal process is performed so that a decrosslinking reaction is generated in the BARC layer on the exposure portions. A development process is performed in order to form photoresist layer patterns and BARC layer patterns by removing the BARC layer at portions in which the decrosslinking reaction has occurred and the exposure portions. A silylation process is performed in order to form silylation patterns on sidewalls of each of the photoresist layer patterns. The BARC layer patterns and the photoresist layer patterns are removed. The etch target layer is patterned using the silylation patterns as an etch mask.Type: ApplicationFiled: December 30, 2008Publication date: July 16, 2009Applicant: Hynix Semiconductor Inc.Inventor: Guee Hwang SIM
-
Publication number: 20090170033Abstract: The present invention relates to a method of forming patterns of a semiconductor device. In aspect of the present invention, a photoresist layer is formed on a semiconductor substrate. Exposure regions are formed in the photoresist layer to which light, which corresponds to an intermediate value of a maximum intensity and a minimum intensity of the light, is irradiated by performing an exposure process. Photoresist patterns are formed by removing the exposure regions.Type: ApplicationFiled: June 27, 2008Publication date: July 2, 2009Applicant: Hynix Semiconductor Inc.Inventors: Woo Yung Jung, Guee Hwang Sim
-
Publication number: 20090142711Abstract: The present invention relates to a method of forming a mask pattern. According to the present invention, a negative photoresist layer is formed over a substrate. Some regions of the negative photoresist layer are exposed. The exposed negative photoresist layers are developed. A positive photoresist layer is formed over the substrate including negative tone working photoresist layers. The substrate is baked so that a hydrogen gas is diffused into the positive photoresist layers at boundary portions of the negative tone working photoresist layers. The positive photoresist layers into which the hydrogen gas is diffused are developed.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Applicant: Hynix Semiconductor Inc.Inventors: Woo Yung Jung, Guee Hwang Sim
-
Publication number: 20090053879Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer and fill the first trench. A second trench is formed by patterning the pad layer and removing an exposed semiconductor substrate, the second trench being formed within the first trench. An ion implantation process is performed on the semiconductor substrate exposed through the second trench.Type: ApplicationFiled: December 5, 2007Publication date: February 26, 2009Applicant: Hynix Semiconductor Inc,Inventor: Guee-Hwang SIM
-
Publication number: 20080268607Abstract: This patent relates to a method of fabricating a semiconductor device. Gate insulating layer patterns and gate electrode layer patterns may be formed over a semiconductor substrate. A photoresist pattern through which part of a region between the gate electrode layer patterns is exposed may be formed over the semiconductor substrate including the gate electrode layer patterns. A passivation film, having an etch rate slower than that of the semiconductor substrate, may be formed on the photoresist pattern. A first trench may be formed in the semiconductor substrate using an etch process by employing the passivation film and the photoresist pattern as an etch mask. An ion implantation process may be performed on the semiconductor substrate in which the first trench is formed.Type: ApplicationFiled: December 21, 2007Publication date: October 30, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Guee Hwang Sim
-
Publication number: 20080081297Abstract: A method of forming a pattern of a semiconductor device includes forming a hard mask layer over a semiconductor substrate and forming a photoresist film pattern over the hard mask layer. An outer portion of the photoresist film pattern is converted into an oxide layer having a first vertical wall, a second vertical wall, and a horizontal wall, wherein an inner portion of the photoresist film pattern is enclosed within the converted oxide layer. At least a portion of the horizontal wall is removed to expose the photoresist film pattern remaining within the converted oxide layer. The exposed photoresist film pattern is removed to form first and second oxide patterns corresponding to the first and second vertical walls, respectively, of the oxide layer. The hard mask layer is patterned using the first and second oxide patterns as etch masks. The semiconductor substrate is etched using the patterned hard mask layer.Type: ApplicationFiled: December 21, 2006Publication date: April 3, 2008Applicant: Hynix Semiconductor Inc.Inventors: Guee Hwang Sim, Woo Yung Jung
-
Publication number: 20080064216Abstract: A method of manufacturing a flash memory device includes providing a substrate having an insulating layer, a first mask layer over the insulating layer, a second mask layer over the first mask layer, a first photoresist pattern over the second mask layer, the first photoresist pattern having a first pitch. A material layer is provided over the first photoresist pattern. The material layer is etched to convert the material layer into a material layer pattern having a second pitch that is less than the first pitch. The second hard mask layer is etched using the material layer pattern to form a second hard mask layer pattern that extends along a first direction. A second photoresist pattern is etched, the second photoresist pattern defining a first region that is not exposed and a second region that is exposed, the second region extending along a second direction that is orthogonal to the first direction.Type: ApplicationFiled: June 29, 2007Publication date: March 13, 2008Applicant: Hynix Semiconductor Inc.Inventors: Guee Hwang Sim, Woo Yung Jung