Patents by Inventor Guendalina CATALANO

Guendalina CATALANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145429
    Abstract: Laser direct structuring, LDS material is molded onto semiconductor dice arranged on die pads in a leadframe and the semiconductor dice are electrically coupled with electrically conductive leads in the leadframe via electrical connections that comprise electrically conductive formations exposed at the front surface of the LDS material, electrically conductive vias between the semiconductor dice and the front surface of the LDS material, as well as electrically conductive lines over the front surface of the LDS material that couple selected ones of the electrically conductive formations with selected ones of the second electrically conductive vias. The electrically conductive vias and lines are provided applying laser beam energy to the front surface of the laser direct structuring material at spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material acting as fiducials.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Riccardo VILLA, Guendalina CATALANO
  • Patent number: 11887959
    Abstract: A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Guendalina Catalano
  • Publication number: 20230386980
    Abstract: A semiconductor die is attached on a die-attachment portion of a substrate such as a leadframe. The semiconductor die has a front surface opposite the substrate and one or more contact pads at the front surface having an outer surface finishing of a first electrically conductive material such as NiPd or Al. An encapsulation of laser direct structuring, LDS material is molded onto the semiconductor die attached on the substrate. Laser beam energy is applied to selected locations of the front surface of the encapsulation of LDS material to activate the LDS material at the selected locations and structure therein electrically conductive formations comprising one or more vias towards the contact pad. The vias comprise a second electrically conductive material that is different from the first electrically conductive material of the outer surface finishing of the contact pad.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 30, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Michele DERAI, Guendalina CATALANO
  • Publication number: 20230369279
    Abstract: A semiconductor die is attached on a die-attachment portion of a planar substrate. A planar electrically conductive clip in mounted onto the semiconductor die. The semiconductor die is sandwiched between the die-attachment portion and the electrically conductive clip. A distal portion of the electrically conductive clip extending away from the semiconductor die is spaced from an electrically conductive lead of the planar substrate by a gap. This gap is filled by a mass of gap-filling material transferred to an upper surface of the electrically conductive lead via Laser Induced Forward Transfer (LIFT) processing. A mass of the gap-filling material is sized and dimensioned to substantially fill the gap.
    Type: Application
    Filed: May 8, 2023
    Publication date: November 16, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Thomas GOTTARDI, Nicoletta MODARELLI, Guendalina CATALANO
  • Publication number: 20230230948
    Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 20, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Roberto TIZIANI, Guendalina CATALANO
  • Publication number: 20230187296
    Abstract: The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 15, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Guendalina CATALANO, Nicoletta MODARELLI
  • Patent number: 11626379
    Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 11, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Roberto Tiziani, Guendalina Catalano
  • Publication number: 20230066285
    Abstract: A semiconductor device comprises: one or more semiconductor dice arranged on a substrate such as a leadframe, an insulating encapsulation of, e.g., LDS material molded onto the semiconductor die or dice arranged on the substrate, the encapsulation having a surface opposite the substrate, and electrically conductive formations (e.g., die-to-lead 181, 182, 183 or die-to-die 201, 202) provided in the encapsulation and coupled to the semiconductor die or dice arranged on the substrate. A tape is laminated onto the surface of the encapsulation opposite the substrate and electrically conductive contacts to the electrically conductive formations extend through the tape laminated onto the encapsulation. The length of the electrically conductive contacts is thus reduced to the thickness of the tape laminated onto the encapsulation, thus facilitating producing, e.g., “vertical” MOSFET power devices having a reduced drain-source “on” resistance, RDSON.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Antonio BELLIZZI, Guendalina CATALANO
  • Publication number: 20220199564
    Abstract: A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Guendalina CATALANO
  • Publication number: 20210305191
    Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 30, 2021
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Roberto TIZIANI, Guendalina CATALANO