Patents by Inventor Guendalina CATALANO
Guendalina CATALANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240332250Abstract: Semiconductor chips are arranged on a first surface of a common electrically conductive substrate having an opposite second surface. The substrate includes adjacent substrate portions having mutually facing sides with sacrificial connecting bars extending between adjacent mutually facing sides. A solderable metallic layer is present on the second surface extending over the sacrificial connecting bars. The solderable metallic layer is selectively removed (by laser ablation or etching, for example) from at least part of the length the sacrificial connecting bars. The common electrically conductive substrate is then cut along the length of the elongate sacrificial connecting bars to provide singulated individual semiconductor devices. Undesired formation of electrically conductive filaments or flakes bridging parts of the substrate intended to be mutually isolated is countered.Type: ApplicationFiled: March 25, 2024Publication date: October 3, 2024Applicant: STMicroelectronics International N.V.Inventors: Antonio BELLIZZI, Guendalina CATALANO
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Publication number: 20240332238Abstract: Laser direct structure (LDS) material is molded onto a semiconductor chip arranged on a substrate. The LDS material has a first thickness between a front surface of the LDS material and the substrate. A portion of the LDS material is removed (with a blade, for instance) to form a cavity having an end wall between the front surface of the LDS material and an electrically conductive formation on the substrate. At the cavity, the LDS material has a second thick ness smaller than the first thickness. Laser beam energy is applied to the LDS material at the end wall of the cavity to structure therein one or more vias that extend between the end wall of the cavity and the electrically conductive formation. The semiconductor chip and the electrically conductive formation are electrically coupled with electrically conductive material grown in the one or more vias laser structured in the LDS material.Type: ApplicationFiled: March 25, 2024Publication date: October 3, 2024Applicant: STMicroelectronics International N.V.Inventors: Guendalina CATALANO, Antonio BELLIZZI, Claudio ZAFFERONI
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Publication number: 20240332033Abstract: A “package-less” integrated circuit semiconductor device is produced by laminating first and second insulating films on opposed first and second surfaces of a semiconductor wafer having semiconductor dice integrated therein. Electrically conductive formations towards die pads of the semiconductor dice are provided in vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer. The semiconductor wafer provided with these electrically conductive formations is singulated at separation lines between neighboring semiconductor dice to produce individual semiconductor devices. Each device has: opposed first and second device surfaces having protective portions of the first and second insulating films laminated thereon, and side surfaces extending between the opposed first and second device surfaces, these side surfaces being left uncovered by the first and second insulating films.Type: ApplicationFiled: March 25, 2024Publication date: October 3, 2024Applicant: STMicroelectronics International N.V.Inventors: Michele DERAI, Guendalina CATALANO
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Publication number: 20240145429Abstract: Laser direct structuring, LDS material is molded onto semiconductor dice arranged on die pads in a leadframe and the semiconductor dice are electrically coupled with electrically conductive leads in the leadframe via electrical connections that comprise electrically conductive formations exposed at the front surface of the LDS material, electrically conductive vias between the semiconductor dice and the front surface of the LDS material, as well as electrically conductive lines over the front surface of the LDS material that couple selected ones of the electrically conductive formations with selected ones of the second electrically conductive vias. The electrically conductive vias and lines are provided applying laser beam energy to the front surface of the laser direct structuring material at spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material acting as fiducials.Type: ApplicationFiled: October 27, 2023Publication date: May 2, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Riccardo VILLA, Guendalina CATALANO
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Patent number: 11887959Abstract: A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material.Type: GrantFiled: December 13, 2021Date of Patent: January 30, 2024Assignee: STMicroelectronics S.r.l.Inventors: Michele Derai, Guendalina Catalano
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Publication number: 20230386980Abstract: A semiconductor die is attached on a die-attachment portion of a substrate such as a leadframe. The semiconductor die has a front surface opposite the substrate and one or more contact pads at the front surface having an outer surface finishing of a first electrically conductive material such as NiPd or Al. An encapsulation of laser direct structuring, LDS material is molded onto the semiconductor die attached on the substrate. Laser beam energy is applied to selected locations of the front surface of the encapsulation of LDS material to activate the LDS material at the selected locations and structure therein electrically conductive formations comprising one or more vias towards the contact pad. The vias comprise a second electrically conductive material that is different from the first electrically conductive material of the outer surface finishing of the contact pad.Type: ApplicationFiled: May 26, 2023Publication date: November 30, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Michele DERAI, Guendalina CATALANO
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Publication number: 20230369279Abstract: A semiconductor die is attached on a die-attachment portion of a planar substrate. A planar electrically conductive clip in mounted onto the semiconductor die. The semiconductor die is sandwiched between the die-attachment portion and the electrically conductive clip. A distal portion of the electrically conductive clip extending away from the semiconductor die is spaced from an electrically conductive lead of the planar substrate by a gap. This gap is filled by a mass of gap-filling material transferred to an upper surface of the electrically conductive lead via Laser Induced Forward Transfer (LIFT) processing. A mass of the gap-filling material is sized and dimensioned to substantially fill the gap.Type: ApplicationFiled: May 8, 2023Publication date: November 16, 2023Applicant: STMicroelectronics S.r.l.Inventors: Thomas GOTTARDI, Nicoletta MODARELLI, Guendalina CATALANO
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Publication number: 20230230948Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.Type: ApplicationFiled: March 28, 2023Publication date: July 20, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Roberto TIZIANI, Guendalina CATALANO
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Publication number: 20230187296Abstract: The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate.Type: ApplicationFiled: December 6, 2022Publication date: June 15, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Guendalina CATALANO, Nicoletta MODARELLI
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Patent number: 11626379Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.Type: GrantFiled: March 11, 2021Date of Patent: April 11, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Roberto Tiziani, Guendalina Catalano
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Publication number: 20230066285Abstract: A semiconductor device comprises: one or more semiconductor dice arranged on a substrate such as a leadframe, an insulating encapsulation of, e.g., LDS material molded onto the semiconductor die or dice arranged on the substrate, the encapsulation having a surface opposite the substrate, and electrically conductive formations (e.g., die-to-lead 181, 182, 183 or die-to-die 201, 202) provided in the encapsulation and coupled to the semiconductor die or dice arranged on the substrate. A tape is laminated onto the surface of the encapsulation opposite the substrate and electrically conductive contacts to the electrically conductive formations extend through the tape laminated onto the encapsulation. The length of the electrically conductive contacts is thus reduced to the thickness of the tape laminated onto the encapsulation, thus facilitating producing, e.g., “vertical” MOSFET power devices having a reduced drain-source “on” resistance, RDSON.Type: ApplicationFiled: August 25, 2022Publication date: March 2, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Antonio BELLIZZI, Guendalina CATALANO
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Publication number: 20220199564Abstract: A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material.Type: ApplicationFiled: December 13, 2021Publication date: June 23, 2022Applicant: STMicroelectronics S.r.l.Inventors: Michele DERAI, Guendalina CATALANO
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Publication number: 20210305191Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.Type: ApplicationFiled: March 11, 2021Publication date: September 30, 2021Applicant: STMICROELECTRONICS S.r.l.Inventors: Roberto TIZIANI, Guendalina CATALANO