Patents by Inventor Guennadi RIGUER

Guennadi RIGUER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12189534
    Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 7, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Saurabh Sharma, Hashem Hashemi, Paavo Pessi, Mika Tuomi, Gianpaolo Tommasi, Jeremy Lukacs, Guennadi Riguer
  • Publication number: 20250005841
    Abstract: A technique for sampling a primitive ID map. The technique includes identifying a sample point having a location in a texture space; obtaining a primitive ID sample from the primitive ID map based on the location of the sample point in the texture space; identifying a primitive based on the primitive ID; testing the location in the texture space for inclusion within the identified primitive; and selecting either the primitive ID or a different primitive ID based on the testing.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michal Adam Wozniak, Guennadi Riguer
  • Publication number: 20250005840
    Abstract: A technique for texture filtering. A transition is made from a first mipmap corresponding to a first texture resolution to a second mipmap corresponding to a second texture resolution. The first texture resolution is lower than the second texture resolution. As compared to standard trilinear filtering, initiation of the transition is delayed by an offset (or bias), which serves to delay the initial use of the second mipmap until it has been loaded. Following initiation of the transition, first and second weightings are selected with a nonlinear filter, and the system interpolates between the first mipmap and the second mipmap by applying the weightings. During an initial portion of the transition, the nonlinear filter has a slope that is higher than that of the standard trilinear filter.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250005838
    Abstract: A technique for rendering is provided. The technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient to obtain a third gradient; and performing anisotropic filtering on the material texture using the third gradient to obtain a value for the shade space texel.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michal Adam Wozniak, Guennadi Riguer
  • Publication number: 20250005849
    Abstract: A technique for rendering is provided. The technique includes determining a first correspondence between a screen space and a shade space in a visibility pass; selecting a size for a shade space tile based on the correspondence between the screen space and the shade space; and shading the shade space tile based on the material texture correspondence.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Patent number: 12182396
    Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: December 31, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Christopher J. Brennan, Akshay Lahiry, Guennadi Riguer
  • Publication number: 20240411706
    Abstract: A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 12, 2024
    Inventors: Saurabh Sharma, Hashem Hashemi, Guennadi Riguer
  • Publication number: 20240329833
    Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Christopher J. Brennan, Akshay Lahiry, Guennadi Riguer
  • Publication number: 20240202862
    Abstract: A processing device and a method of auto-tiled workload processing is provided. The processing device includes memory and a processor. The processor is configured to store instructions for operations to be executed on an image to be divided into a plurality of tiles, store information associated with the operations, select one of the operations for execution and execute an auto-tiling plan for the operation based on the information associated with the operations. The auto-tiling plan comprises, for example, determining a number of tiles used to divide the image and determining a size of one or more of the tiles of the image.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Mark Satterthwaite, Jeremy Lukacs, Zhuo Chen, Gareth Havard Thomas
  • Patent number: 11711571
    Abstract: A server offloads graphics effects processing to a client device with graphics processing resources by determining a modification to a graphics effects operation, generating a portion of a rendered video stream using the modification to the graphics effects operation, and providing an encoded representation of the portion of the rendered video stream to the client device, along with metadata representing the modification implemented. The client device decodes the encoded representation to recover the portion of the rendered video stream and selectively performs a graphics effects operation on the recovered portion to at least partially revert the resulting graphics effects for the portion to the intended effects without the modification implemented by the server.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 25, 2023
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Ihab Amer, Guennadi Riguer, Thomas Perry, Mehdi Saeedi, Gabor Sines, Yang Liu
  • Publication number: 20230205698
    Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Inventors: Saurabh SHARMA, Hashem HASHEMI, Paavo PESSI, Mika TUOMI, Gianpaolo TOMMASI, Jeremy LUKACS, Guennadi RIGUER
  • Publication number: 20230195509
    Abstract: A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Saurabh Sharma, Jeremy Lukacs, Hashem Hashemi, Gianpaolo Tommasi, Guennadi Riguer, Mark Fowler, Randy Ramsey
  • Publication number: 20230195626
    Abstract: A processing system is configured to translate a first cache access pattern of a dispatch of work items to a cache access pattern that facilitates consumption of data stored at a cache of a parallel processing unit by a subsequent access before the data is evicted to a more remote level of the memory hierarchy. For consecutive cache accesses having read-after-read data locality, in some embodiments the processing system translates the first cache access pattern to a space-filling curve. In some embodiments, for consecutive accesses having read-after-write data locality, the processing system translates a first typewriter cache access pattern that proceeds in ascending order for a first access to a reverse typewriter cache access pattern that proceeds in descending order for a subsequent cache access. By translating the cache access pattern based on data locality, the processing system increases the hit rate of the cache.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Saurabh Sharma, Jeremy Lukacs, Hashem Hashemi, Gianpaolo Tommasi, Guennadi Riguer, Mark Fowler, Randy Ramsey
  • Patent number: 11620724
    Abstract: Some implementations provide systems, devices, and methods for implementing a cache replacement policy. A memory request is issued for attribute information associated with a node in an acceleration data structure. The attribute information associated with the node is inserted into a cache entry of the cache and an age associated with the cache entry is set to a value based on the attribute information, in response to the memory request causing a cache miss.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 4, 2023
    Assignee: ATI Technologies ULC
    Inventor: Guennadi Riguer
  • Publication number: 20230097620
    Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.
    Type: Application
    Filed: December 2, 2022
    Publication date: March 30, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies UL
    Inventors: Guennadi Riguer, Brian K. Bennett
  • Patent number: 11521293
    Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 6, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Brian K. Bennett
  • Patent number: 11474591
    Abstract: Systems, apparatuses, and methods for implementing fine-grain power management for virtual reality (VR) systems are disclosed. A VR compositor monitors workload tasks while rendering and displaying content of a VR application. The VR compositor determines the priorities of different tasks of a given VR frame and cause power states to be assigned to processing units to match the priorities of the tasks being performed. For example, if a first task within a first frame period is assigned a high priority, a processing unit executing the task operates at a relatively high power performance state when performing the first task. If a second task within the first frame period is assigned a low priority, the processing unit operates at a relatively low power performance state when performing the second task. By implementing fine-grain power management in a VR environment, the likelihood of the processing unit suffering a thermal event or impaired performance is reduced.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 18, 2022
    Assignee: ATI Technologies ULC
    Inventor: Guennadi Riguer
  • Patent number: 11474354
    Abstract: Various virtual reality computing systems and methods are disclosed. In one aspect, a method of delivering video frame data to multiple VR displays is provided. The method includes generating content for multiple VR displays and sensing for competing needs for resources with real time requirements of the multiple VR displays. If competing needs for resources with real time requirements are sensed, a selected refresh offset for refreshes of the multiple VR displays is determined to avoid conflict between the competing needs for resources of the multiple VR displays. The selected refresh offset is imposed and the content is delivered to the multiple VR displays.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 18, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: Guennadi Riguer
  • Patent number: 11450058
    Abstract: Techniques for performing ray tracing operations are provided. The techniques include receiving a request to determine whether a ray intersects any primitive of a set of primitives, evaluating the ray against non-leaf nodes of a bounding volume hierarchy to determine whether to eliminate portions of the bounding volume hierarchy from consideration, evaluating the ray against at least one early-termination node not eliminated from consideration, and determining whether to terminate traversal of the bounding volume hierarchy early and to identify that the ray hits a primitive, based on the result of the evaluation of the ray against the at least one early-termination node.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 20, 2022
    Assignee: ATI Technologies ULC
    Inventor: Guennadi Riguer
  • Patent number: 11307655
    Abstract: Systems, apparatuses, and methods for using a multi-stream foveal display transport layer are disclosed. A virtual reality (VR) system includes a transmitter sending a plurality of streams over a display transport layer to a receiver coupled to a display. Each stream corresponds to a different image to be blended together by the receiver. The images include at least a foveal region image corresponding to a gaze direction of the eye and a background image which is a lower-resolution image with a wider field of view than the foveal region image. The phase timing of the foveal region stream being sent over the transport layer is adjusted with respect to the background stream to correspond to the location of the foveal region within the overall image. This helps to reduce the amount of buffering needed at the receiver for blending the images together to create a final image to be driven to the display.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 19, 2022
    Assignee: ATI Technologies ULC
    Inventors: Guennadi Riguer, Syed Athar Hussain