Patents by Inventor Guennadi RIGUER

Guennadi RIGUER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111598
    Abstract: A technique for rendering is provided. The technique includes performing a visibility operation to generate shade space visibility information and reconstruction information; performing a shade space shading operation based on the shade space visibility information generate shaded shade space textures; and performing a reconstruction operation based on the reconstruction information and the shaded shade space textures.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michal Adam Wozniak, Guennadi Riguer
  • Publication number: 20250111600
    Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatially-adaptive sampling; performing a sparse shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatially-adaptive sampling; performing a regularization operation based on an output of the sparse shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250111582
    Abstract: A technique for rendering is provided. The technique includes determining a level of detail for a shade space texture and a screen space; shading the shade space texture having a resolution based on the level of detail; and for a reconstruction operation, performing sampling from the shade space texture, the sampling including a high frequency attenuation of samples of the shade space texture.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Boris Ivanovic, Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250111601
    Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatiotemporal adaptive sampling; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatiotemporal adaptive sampling; performing a regularization operation based on an output of the shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250111461
    Abstract: A processing system includes two or more graphics cores each disposed on respective dies and configured for concurrent processing of command packets. To this end, the processing system is configured to determine two or more command partitions associated with a command packet and to assign each command partition to a graphics core. Each graphics core then executes the same command packet by only performing instructions of the command packet associated with the command partitions assigned to the graphics core. Further, after executing an instructions of the command packet based on one or more assigned partitions, each graphics core adjusts one or more counters used to synchronize the execution of the command packet across the graphics cores.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Alexander Fuad Ashkar, Guennadi Riguer, Nishank Pathak
  • Publication number: 20250111599
    Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover the shade space textures visible in the scene; performing a temporal rate controller operation; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a temporal shading rate output by the temporal rate controller operation, wherein only a subset of samples in the tiles that cover the shade space textures visible in the scene are shaded in the shade space shading operation; and performing a reconstruction operation using output from the shade space shading operation to produce a final scene.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250077379
    Abstract: Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.
    Type: Application
    Filed: September 4, 2023
    Publication date: March 6, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Christopher J. Brennan
  • Patent number: 12216590
    Abstract: A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: February 4, 2025
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Saurabh Sharma, Hashem Hashemi, Guennadi Riguer
  • Patent number: 12189534
    Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 7, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Saurabh Sharma, Hashem Hashemi, Paavo Pessi, Mika Tuomi, Gianpaolo Tommasi, Jeremy Lukacs, Guennadi Riguer
  • Publication number: 20250005840
    Abstract: A technique for texture filtering. A transition is made from a first mipmap corresponding to a first texture resolution to a second mipmap corresponding to a second texture resolution. The first texture resolution is lower than the second texture resolution. As compared to standard trilinear filtering, initiation of the transition is delayed by an offset (or bias), which serves to delay the initial use of the second mipmap until it has been loaded. Following initiation of the transition, first and second weightings are selected with a nonlinear filter, and the system interpolates between the first mipmap and the second mipmap by applying the weightings. During an initial portion of the transition, the nonlinear filter has a slope that is higher than that of the standard trilinear filter.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250005838
    Abstract: A technique for rendering is provided. The technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient to obtain a third gradient; and performing anisotropic filtering on the material texture using the third gradient to obtain a value for the shade space texel.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michal Adam Wozniak, Guennadi Riguer
  • Publication number: 20250005849
    Abstract: A technique for rendering is provided. The technique includes determining a first correspondence between a screen space and a shade space in a visibility pass; selecting a size for a shade space tile based on the correspondence between the screen space and the shade space; and shading the shade space tile based on the material texture correspondence.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250005841
    Abstract: A technique for sampling a primitive ID map. The technique includes identifying a sample point having a location in a texture space; obtaining a primitive ID sample from the primitive ID map based on the location of the sample point in the texture space; identifying a primitive based on the primitive ID; testing the location in the texture space for inclusion within the identified primitive; and selecting either the primitive ID or a different primitive ID based on the testing.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michal Adam Wozniak, Guennadi Riguer
  • Patent number: 12182396
    Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: December 31, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Christopher J. Brennan, Akshay Lahiry, Guennadi Riguer
  • Publication number: 20240411706
    Abstract: A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 12, 2024
    Inventors: Saurabh Sharma, Hashem Hashemi, Guennadi Riguer
  • Publication number: 20240329833
    Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Christopher J. Brennan, Akshay Lahiry, Guennadi Riguer
  • Publication number: 20240202862
    Abstract: A processing device and a method of auto-tiled workload processing is provided. The processing device includes memory and a processor. The processor is configured to store instructions for operations to be executed on an image to be divided into a plurality of tiles, store information associated with the operations, select one of the operations for execution and execute an auto-tiling plan for the operation based on the information associated with the operations. The auto-tiling plan comprises, for example, determining a number of tiles used to divide the image and determining a size of one or more of the tiles of the image.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Mark Satterthwaite, Jeremy Lukacs, Zhuo Chen, Gareth Havard Thomas
  • Patent number: 11711571
    Abstract: A server offloads graphics effects processing to a client device with graphics processing resources by determining a modification to a graphics effects operation, generating a portion of a rendered video stream using the modification to the graphics effects operation, and providing an encoded representation of the portion of the rendered video stream to the client device, along with metadata representing the modification implemented. The client device decodes the encoded representation to recover the portion of the rendered video stream and selectively performs a graphics effects operation on the recovered portion to at least partially revert the resulting graphics effects for the portion to the intended effects without the modification implemented by the server.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 25, 2023
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Ihab Amer, Guennadi Riguer, Thomas Perry, Mehdi Saeedi, Gabor Sines, Yang Liu
  • Publication number: 20230205698
    Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Inventors: Saurabh SHARMA, Hashem HASHEMI, Paavo PESSI, Mika TUOMI, Gianpaolo TOMMASI, Jeremy LUKACS, Guennadi RIGUER
  • Publication number: 20230195509
    Abstract: A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Saurabh Sharma, Jeremy Lukacs, Hashem Hashemi, Gianpaolo Tommasi, Guennadi Riguer, Mark Fowler, Randy Ramsey