Patents by Inventor Guenter Igel
Guenter Igel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7166232Abstract: According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated into the substrate regions not covered by the masking layer (6). A heat treatment is used to diffuse the substance into a substrate region covered by the masking layer (6) such that a concentration gradient of the substance is created in the substrate region covered by the masking layer (6), proceeding from the edge of the masking layer (6) inward with increasing distance from the edge. The masking layer (6) is then removed to expose the substrate region under this layer, and a near-surface layer of the substrate (3) in the exposed substrate region is converted by a chemical conversion reaction into a coating (9) which has a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.Type: GrantFiled: December 21, 2000Date of Patent: January 23, 2007Assignee: Micronas GmbHInventors: Guenter Igel, Mirko Lehmann
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Patent number: 6425289Abstract: A capacitive sensor is described which includes a first electrode remote from a second electrode, wherein the first electrode and the second electrode form a measurement capacitance. The first electrode is arranged on a first substrate member and the second electrode is arranged on a second substrate member. At least one of the electrodes has a spatially resolved structure which allows a spatially resolved measurement of the capacitance. The spatial structure of the electrode may be implemented in form of several mutually parallel stripe-shaped elements or in form of a plurality of spaced-apart elements that are arranged in a two-dimensional pattern. Associated with the electrodes are electronic processing units integrated in the substrate members.Type: GrantFiled: April 16, 1999Date of Patent: July 30, 2002Assignee: Micronas GmbHInventors: Guenter Igel, Ulrich Sieben, Juergen Giehl
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Patent number: 6370960Abstract: A capacitive sensor including a first electrode and a second electrode which are disposed opposite each other in spaced-apart relationship to form a capacitor, the first electrode being disposed on a first substrate and the second electrode on a second substrate, the substrates being joined together at the sides of the electrodes, and the second substrate forming, in the area of the second electrode, a diaphragm deformable by pressure. An electronic signal processing device for processing the measurement signals is incorporated in one of the substrates below the electrode disposed thereon.Type: GrantFiled: April 19, 1999Date of Patent: April 16, 2002Assignee: Micronas Internmetall GmbHInventors: Guenter Igel, Ulrich Sieben, Juergen Giehl
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Patent number: 6204549Abstract: The invention relates to an overvoltage protection device and to a method for fabricating such a device. A substrate (1) is provided with a first electrode layer (2), above which extends a second electrode layer (3) which is separated from the first electrode layer (2) by a distance (d) determined by the thickness of a spacing layer (4). The spacing layer (4) has an opening (5) which forms a cavity (6) between the electrode layers (2, 3).Type: GrantFiled: August 21, 1998Date of Patent: March 20, 2001Assignee: Micronas Intermetall GmbHInventors: Guenter Igel, Joachim Krumrey
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Patent number: 6127268Abstract: A process is disclosed for fabricating a semiconductor device with a patterned metal layer (9). A layer (7) of a material with poor adhesion capability to the metal is deposited on the surface of a semiconductor substrate. On the layer (7), pattern lines (8) separated by a distance a are formed of a material with good adhesion capability to the metal, and the metal layer (9) is deposited such that by suitable choice of the ratio of the distance a to its thickness d and of its material properties, the metal layer (9) is caused to adhere only to the pattern lines (8) and to the area of the layer (7) between the pattern lines (8).Type: GrantFiled: June 11, 1998Date of Patent: October 3, 2000Assignee: Micronas Intermetall GmbHInventor: Guenter Igel
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Patent number: 6127274Abstract: There is disclosed a process for producing electronic devices from a semiconductor wafer. The process comprises forming separation regions with a spatial pattern on the semiconductor wafer to provide separation between electronic devices, and depositing a conductive contact layer on the wafer and patterning the contact layer in such a way that conductive terminals extend from the front side of the wafer over at least part of the cross section of the patterned separation regions. The terminals are bared by removing material of the wafer in the semiconductor regions starting from the backside of the wafer, and the terminals of adjacent electronic devices are separated.Type: GrantFiled: February 25, 1998Date of Patent: October 3, 2000Assignee: Micronas Intermetall GmbHInventors: Guenter Igel, Martin Mall
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Patent number: 6028009Abstract: A process is disclosed for fabricating a device with a cavity formed at one end thereof. A body is provided with a depression, and mask layer is applied to the surface of the body and the depression, the mask layer having a lower etch rate than the body. Near the depression, an opening is formed in the mask layer. Starting from the opening, the body is subjected to an isotropic etching process to form the cavity below the mask layer, with the mask layer being essentially preserved and forming in the area of the depression a structure extending into the cavity.Type: GrantFiled: April 16, 1998Date of Patent: February 22, 2000Assignee: Micronas Intermetall GmbHInventors: Guenter Igel, Martin Mall
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Patent number: 6017775Abstract: The invention relates to a process for manufacturing a sensor with a metal electrode in an MOS structure. During the MOS process, a sensing region with a structure for the metal electrode is formed, this structure being made of a material having predetermined adhesion properties for metals, the sensing region being uncovered by etching the passivating layer, and a metallization of the surface of the MOS structure being carried out in which the metal layer adheres only to the structure for the metal electrode.Type: GrantFiled: October 9, 1997Date of Patent: January 25, 2000Assignee: Micronas Intermetall GmbHInventors: Guenter Igel, Hans-Jurgen Gahle
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Patent number: 5902120Abstract: A process is disclosed for producing spatially patterned components from a body. On the backside of the body, a retardation layer with openings is provided for retarding a removal of the material of the body, and areas of migration-capable material are deposited. The body is subjected to a thermal migration process to form migration regions. Then, in a single material removal step, the components are separated from the body and the migration regions are exposed.Type: GrantFiled: March 13, 1998Date of Patent: May 11, 1999Assignee: Micronas Intermetall GmbHInventors: Guenter Igel, Martin Mall
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Patent number: 5888882Abstract: A process for separating electronic devices connected with one another in a body, the process including thinning the side of the body remote from the electronic devices, separating the electronic devices, and testing electrical parameters of the electronic devices after the thinning of the body. The handling of the body is improved by applying to the side of the body containing the electronic devices, prior to the thinning process, an electrically nonconductive auxiliary layer in which respective contact openings are formed above the electronic devices to expose the contact(s) of the respective electronic device.Type: GrantFiled: April 4, 1997Date of Patent: March 30, 1999Assignee: Deutsche ITT Industries GmbHInventors: Guenter Igel, Martin Mall
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Patent number: 5814874Abstract: A semiconductor device having a semiconductor substrate and an epitaxial layer deposited thereon which supports a patterned insulating layer on which a metal layer is provided. To achieve a lower capacitance of the semiconductor device with unchanged forward voltage, the epitaxial layer consists of first and second epitaxial layers, the first epitaxial layer which adjoins the semiconductor substrate having a higher dopant concentration than and being of the same conductivity type as the second epitaxial layer.Type: GrantFiled: July 16, 1996Date of Patent: September 29, 1998Assignee: General Semiconductor IrelandInventor: Guenter Igel