Patents by Inventor Guenter Pfeifer

Guenter Pfeifer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8796089
    Abstract: An embodiment relates to a method of forming a semiconductor structure, comprising: forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a third semiconductor layer over the second semiconductor layer; forming an opening in the first, second and third semiconductor layers; forming a conductive region within the first, the and third semiconductor layer, the conductive region surrounding the opening, the conductive region being electrically coupled to the first semiconductor layer; forming a dielectric layer in the opening and over the conductive region; and forming a conductive layer over the dielectric layer in the opening.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 5, 2014
    Assignee: Infineon Technologies AG
    Inventors: Detlef Wilhelm, Guenter Pfeifer, Bernd Eisener, Dieter Claeys
  • Publication number: 20140080280
    Abstract: An embodiment relates to a method of forming a semiconductor structure, comprising: forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a third semiconductor layer over the second semiconductor layer; forming an opening in the first, second and third semiconductor layers; forming a conductive region within the first, the and third semiconductor layer, the conductive region surrounding the opening, the conductive region being electrically coupled to the first semiconductor layer; forming a dielectric layer in the opening and over the conductive region; and forming a conductive layer over the dielectric layer in the opening.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Inventors: Detlef WILHELM, Guenter PFEIFER, Bernd EISENER, Dieter CLAEYS
  • Patent number: 8592883
    Abstract: An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Dieter Claeys, Bernd Eisener, Guenter Pfeifer, Detlef Wilhelm
  • Publication number: 20130069198
    Abstract: An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 21, 2013
    Inventors: Dieter Claeys, Bernd Eisener, Guenter Pfeifer, Detlef Wilhelm