Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

Abstract: A semiconductor system for a current sensor in a power semiconductor includes: on a substrate, a multiple arrangement of transistor cells having an insulated gate electrode, whose emitter terminals are connected in a first region via a first conductive layer to at least one output terminal and whose emitter terminals are connected in a second region via a second conductive layer to at least one sensor terminal, which is situated outside of a first cell region boundary, which encloses the transistor cells of the first region and the second region, a trench structure belonging to the first cell region boundary being developed between the transistor cells of the second region and the sensor terminal.

Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

Abstract: Known methods for forming trench storage capacitors require the chemical vapour deposition (CVD) of an undoped silicon oxide layer in order to prevent auto doping of side wall of a semiconductor trench. This layer is deposited once an arsenic doped silicon oxide layer has been disposed and etched to an appropriate depth. Such a technique results in a complex and expensive process. It is therefore proposed to deposit (step 906) the undoped silicon oxide layer 108 in-situ immediately after the arsenic doped silicon oxide layer 106 has been deposited (step 904) and before etching takes place (step 910). It is thus possible to remove the CVD of the undoped silicon oxide, thereby simplifying the overall process and yielding a device having improved performance characteristics.

Abstract: A process for DRAM cell production includes (1) depositing a layer of a first substance in a trench; (2) depositing a first layer of a second substance in said trench; (3) growing an interfacial layer of oxide between said layer of said first substance and said first layer of said second substance, and between side walls of said trench and said first layer of said second substance; (4) applying an anisotropic etching substance to the surface of said first layer of said second substance, thereby exposing said interfacial layer of oxide; (5) applying a second etching substance to the surface of said first layer of said second substance thereby substantially removing said interfacial layer of oxide; and (6) depositing a second layer of said second substance in said trench. The process reduces the contact resistance of the buried strap and improves the production yield for low temperature performance cells.