Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

Abstract: The semiconductor device comprises a semiconductor substrate (2), a transition layer (5) in or on the semiconductor substrate, the transition layer allowing propagation of incident radiation (7) according to a refractive index, and a photonic component (4) facing the transition layer. A surface (6) of the transition layer is structured such that the effective refractive index is gradually changed through the transition layer with changing distance from the photonic component.

Abstract: The method comprises the steps of providing a semiconductor body or substrate (1) with a recess or trench (2) in a main surface (10), applying a mask (3) on the main surface, the mask covering the recess or trench, so that the walls and bottom of the recess or trench and the mask together enclose a cavity (4), which is filled with a gas, and forming at least one opening (5) in the mask at a distance from the recess or trench, the distance (6) being adapted to allow the gas to escape from the cavity via the opening when the gas pressure exceeds an external pressure.

Abstract: A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.

Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a contact hole (2) reaching from a surface (10) into the substrate, and a contact metallization (12) arranged in the contact hole, so that the contact metallization forms an internal substrate contact (4) on the semiconductor material at least in a bottom area (40) of the contact hole.

Abstract: The method comprises the steps of providing a semiconductor body or substrate (1) with a recess or trench (2) in a main surface (10), applying a mask (3) on the main surface, the mask covering the recess or trench, so that the walls and bottom of the recess or trench and the mask together enclose a cavity (4), which is filled with a gas, and forming at least one opening (5) in the mask at a distance from the recess or trench, the distance (6) being adapted to allow the gas to escape from the cavity via the opening when the gas pressure exceeds an external pressure.

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a contact hole (2) reaching from a surface (10) into the substrate, and a contact metallization (12) arranged in the contact hole, so that the contact metallization forms an internal substrate contact (4) on the semiconductor material at least in a bottom area (40) of the contact hole.

Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).

Abstract: A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.

Abstract: In an insulation layer of an SOI substrate, a connection pad is arranged. A contact hole opening above the connection pad is provided on side walls and on the connection pad with a metallization that is contacted on top side with a top metal.

Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).

Abstract: In the insulation layer (2) of an SOI substrate (1), a connection pad (7) is arranged. A contact hole opening (9) above the connection pad is provided on side walls and on the connection pad with a metallization (11) that is contacted on the top side with a top metal (12).

Abstract: A polysilicon layer provided for a polysilicon electrode (8) is patterned by means of a resist mask (5) and an auxiliary layer (4) made of a material that is suitable as an antireflection layer, the auxiliary layer (4) being provided with lateral hollowed-out recesses in such a way that the polysilicon electrode is formed with rounded edges (7) during etching. The auxiliary layer is preferably produced from a soluble material and with a thickness of 70 nm to 80 nm. A base layer (2) may be provided as a gate dielectric of memory cell transistors and additionally as an etching stop layer.

Abstract: A polysilicon layer provided for a polysilicon electrode (8) is patterned by means of a resist mask (5) and an auxiliary layer (4) made of a material that is suitable as an antireflection layer, the auxiliary layer (4) being provided with lateral hollowed-out recesses in such a way that the polysilicon electrode is formed with rounded edges (7) during etching. The auxiliary layer is preferably produced from a soluble material and with a thickness of 70 nm to 80 nm. A base layer (2) may be provided as a gate dielectric of memory cell transistors and additionally as an etching stop layer.

Abstract: A silicon substrate includes plural partial areas defined on the silicon substrate such that adjacent partial areas are orientated in different directions. The plural partial areas define an insulating layer that extends from a surface of the silicon subtrate into the silicon substrate. Each of the plural partial areas includes first regions that contain silicon dioxide formed by oxidation of silicon in the silicon substrate, and second regions that contain silicon dioxide deposited onto the silicon substrate. The first regions and the second regions are oriented in a substantially same direction and are arranged side-by-side and alternately such that two first regions do not border and two second regions do not border.