Abstract: A method for adjusting the rate of a horological module, said horological module including a printed circuit (1) on which are mounted in particular a quartz (10) and an integrated circuit (20) including an oscillator (21) driven by the quartz (10), a frequency divider circuit (22) with several stages (22.1 to 22.15), an adjustment circuit (23) allowing the introduction of a correction factor of the division ratio of said frequency divider circuit (22), and a memory circuit (24) containing data (N) representing said correction factor. The adjustment method according to the present invention uses a laser device to allow said data (N) representing the correction factor to be coded by the selective destruction of fuses (F1, F2; F.1 to F.6; F.1* to F.6*) forming memory elements of said memory circuit (24).

Abstract: A CCD arrangement which includes a semiconductor layer of a first conductivity type, a layer of insulating material on the semiconductor layer, a row of shift electrodes on the insulating layer. The row of shift electrodes on the insulating layer are fed with pulse train voltages displaced in phase relative to one another. The charges are fed to an output end diffusion zone of the opposite conductivity type which has previously been brought to a reference potential and then released from the latter producing a state which is not bound in potential to the exterior. One of the shift electrodes is connected via a terminal to a transistor switch which intermittently supplies the assigned pulse train voltage, and to the gate of a field effect capacitor whose counter electrode is fed with a periodic pulse voltage. The rising flanks of this pulse voltage are each delayed relative to the times at which the assigned pulse train voltage is interrupted.

Abstract: A dynamic storage element has an electrically insulating layer carried on a substrate of semiconductor material. A conductor path, provided with a terminal, is arranged on the electrically insulating layer, and first and second zones, doped oppositely to the substrate, are provided on the surface of the substrate. The zones are spaced from one another. In that region of the substrate between the zones the substrate is more highly doped with dopants of the same type as those contained in the substrate and the conductor path extends above the highly doped region.

Abstract: A monolithic integrated circuit arrangement is disclosed which is formed of a group of one-transistor storage elements arranged on a semiconductor layer. Each storage element has a selection field effect transistor and a storage capacitor. The storage elements are arranged in pairs. First and second storage capacitors of each pair are combined to save storage area. In one embodiment, a first conductive coating overlying a surface of the semiconductor layer is employed as a common second electrode for all the storage capacitors. Additional second conductive coatings insulated from the first conductive coating and arranged thereover form the first electrodes for the storage capacitors. In another embodiment a first conductive coating is employed as a common second electrode for the storage capacitors. A second conductive coating is utilized as a first electrode for some of the storage electrodes while an inversion or diffusion layer is utilized as a first electrode for the other storage capacitors.

Abstract: Regenerator circuit for CCD elements in which charge representing information is transferred from a first CCD element to a second CCD element. The circuit includes a first MOS capacitance and a second capacitance connected in series with the first capacitance, the point at which the two capacitances are connected with one another being connected to the input of said second CCD. The output of the first CCD includes an output stage having an output diffusion zone. A transistor is connected between a terminal to which a potential .phi..sub.v can be connected and the point between said first and second capacitances. This transistor has a gate electrode which is connected by a line to the output diffusion zone of the first CCD.

Abstract: A process for producing an integrated circuit having a pair of complementary field effect transistors, one being a J-FET and the other being a MIS-FET. The process includes a series of masking and ion implantation steps carried out in part for both transistors at the same time. The doping of the region between the source and drain is increased for the MIS-FET at the same time that the doping of the channel of the J-FET is increased in order to control the threshold voltage of the MIS-FET.

Abstract: A compensation element and method for operating the same, for use with dynamic semiconductor stores, employing a main storage element operatively connected to a word line and a bit line, and an evaluator circuit operatively connected to the bit line, by means of which the storage element may be read out, comprising the steps of capacitively coupling a correcting voltage to the bit line which may be selectively applied thereto in response to signals on a compensation-selector line operative to control the application of said correcting voltage to the bit line whereby the same is raised to the most favorable middle potential of U.sub.BD =0.5 (U.sub.BO + U.sub.Bl), in which U.sub.BO = read outvoltage resulting from storage of a binary "0", and U.sub.Bl = read out voltage resulting from storage of a binary "1".