Abstract: The invention relates to a method for treating chlamydial infections in mammals and humans. According to the invention, tissue material containing clamydia is heated to temperatures of greater than 50° C., preferably 80-85° C., for 1-5 hours in the presence of agents, preferably formaldehyde or p-formaldehyde, which cross-link proteins.

Abstract: Storage hierarchy comprising a main store with user and program data (L), a control store with micro code (C), and a processor buffer store which is commonly used for both data types (L & C). With no restrictions imposed, allocation of buffer space for L and C type data is self-adapting, since the address and replacement array are used jointly for both types of data.Alternatively, to reserve at least a minimum amount of buffer space for L and C type blocks, respectively, one or two space limit values may be defined and adhered to each time buffer block space is allocated anew. Thus the buffer space may be shared by the two types of data either in a fully overlapping (no space limit values), in a partly overlapping (two space limit values) or in a non-overlapping manner (one space limit value).

Abstract: Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.

Abstract: For increasing the availability of a modular computer, a control unit and switches are provided, the latter being connected in between the control storages and the remaining identical hardware of the processor. In the case of a hardware error of one processor, its control storage is switched for a specific period of time to the same hardware of another processor which interrupts its own tasks, assuming the tasks of the defective processor for the time during which the control storage of the defective processor remains switched off. Subsequently, the former or non-defective processor resumes its own tasks. The task cycles assigned to one processor or the other can be specified to be identical or as a function of the respective processing requirements.