Patents by Inventor Gueron Shay

Gueron Shay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119123
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119131
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119125
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119124
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119128
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119130
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119127
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119126
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119129
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis