Patents by Inventor Gugliemo Sirna

Gugliemo Sirna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6476668
    Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor (Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: November 5, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Ranjit Gharpurey, Gugliemo Sirna
  • Publication number: 20020153955
    Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively.
    Type: Application
    Filed: March 1, 2001
    Publication date: October 24, 2002
    Inventors: Ranjit Gharpurey, Gugliemo Sirna
  • Patent number: 6452456
    Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor(Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: September 17, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Ranjit Gharpurey, Gugliemo Sirna
  • Publication number: 20020121936
    Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 5, 2002
    Inventors: Ranjit Gharpurey, Gugliemo Sirna