Patents by Inventor Gui Fu
Gui Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966726Abstract: A method, computer program product, and computer system are provided. An enhanced compiler identifies instructions for execution among them, instructions directed to an inner computation unit of a CPU core. In response to identifying instructions directed to the inner computation unit, locating in a system call table a system call to indicate a begin of an executable code block of instructions that are directed to the inner computation unit of the CPU core. The enhanced compiler searches the system hardware registry for the parameter corresponding to the inner computation unit of the CPU core. The system call is inserted as an interrupt instruction in the compiler output at the begin of the executable code block of instructions that are directed to the inner computation unit of the CPU core. The enhanced compiler executable code output is saved for later selection by a scheduler of an operating system.Type: GrantFiled: February 25, 2022Date of Patent: April 23, 2024Assignee: International Business Machines CorporationInventors: Zheng Chen, Jiu Fu Guo, Gui HaoChen, Chaofan Qiu
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Publication number: 20220407725Abstract: Embodiments of the present disclosure disclose a file storage method, terminal, and storage medium. The file storage method includes: obtaining a to-be-stored file, performing splitting processing on the to-be-stored file to obtain N sub-files corresponding to the to-be-stored file, wherein N is an integer greater than or equal to 1; sending the N sub-files to an IPFS, and receiving M pieces of address information corresponding to the N sub-files returned by the IPFS, wherein M is an integer greater than or equal to 1 and less than or equal to N; generating an address set corresponding to the to-be-stored file according to the M pieces of address information, and encrypting the address set to obtain an address set ciphertext; sending the address set ciphertext to a blockchain network and receiving a target index value returned by the blockchain network, wherein the target index value is used to identify the address set ciphertext.Type: ApplicationFiled: March 4, 2020Publication date: December 22, 2022Inventors: Penghui CHAI, Gui FU
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Patent number: 11451430Abstract: Systems and methods for controlling management operations and shared memory space are disclosed. A cloud cache management controller may receive multiple sets of service attributes. Each set of the multiple sets of service attributes may be related to a cloud cache service instance. The cloud cache management controller may receive a first cloud cache management request. The cloud cache management request may comprise a cloud cache management operation. The cloud cache management controller may retrieve a set of service attributes from the multiple sets of service attributes based on an evaluation of the cloud cache management operation. The cloud cache management controller may send the first cloud cache management request to a corresponding CCSI based on a priority value for the first cloud cache management request calculated based on the retrieved set of service attributes.Type: GrantFiled: July 6, 2020Date of Patent: September 20, 2022Assignee: Huawei Cloud Computing Technologies Co., Ltd.Inventors: Ming Chen, Gui Fu, Zhenhua Hu, Heng Kuang, Shaohui Xu, Zhi Zhao
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Patent number: 10951532Abstract: Systems and methods for rate limiting one or more clusters of service instances using at least one rate limit controller are described herein. A token distribution is determined for each one of a plurality of rate limiters. The token distribution comprising a maximum number of tokens and a token generating rate. The maximum number of tokens and the token generating rate are assigned to each one of the plurality of rate limiters. At least one request for additional tokens is received from at least a given one of the plurality of rate limiters. The token distribution of at least the given one of the plurality of rate limiters is adjusted based on the request and on token consumption information of at least the given one of the plurality of rate limiters. An adjusted token distribution is assigned to the given one of the plurality of rate limiters.Type: GrantFiled: July 18, 2018Date of Patent: March 16, 2021Assignee: Huawei Technologies Co., Ltd.Inventors: Hongwu Chen, Gui Fu, Zhenhua Hu, Zhike Zhang
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Publication number: 20200344110Abstract: Systems and methods for controlling management operations and shared memory space are disclosed. A cloud cache management controller may receive multiple sets of service attributes. Each set of the multiple sets of service attributes may be related to a cloud cache service instance. The cloud cache management controller may receive a first cloud cache management request. The cloud cache management request may comprise a cloud cache management operation. The cloud cache management controller may retrieve a set of service attributes from the multiple sets of service attributes based on an evaluation of the cloud cache management operation. The cloud cache management controller may send the first cloud cache management request to a corresponding CCSI based on a priority value for the first cloud cache management request calculated based on the retrieved set of service attributes.Type: ApplicationFiled: July 6, 2020Publication date: October 29, 2020Inventors: Ming Chen, Gui Fu, Zhenhua Hu, Heng Kuang, Shaohui Xu, Zhi Zhao
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Publication number: 20200028788Abstract: Systems and methods for rate limiting one or more clusters of service instances using at least one rate limit controller are described herein. A token distribution is determined for each one of a plurality of rate limiters. The token distribution comprising a maximum number of tokens and a token generating rate. The maximum number of tokens and the token generating rate are assigned to each one of the plurality of rate limiters. At least one request for additional tokens is received from at least a given one of the plurality of rate limiters. The token distribution of at least the given one of the plurality of rate limiters is adjusted based on the request and on token consumption information of at least the given one of the plurality of rate limiters. An adjusted token distribution is assigned to the given one of the plurality of rate limiters.Type: ApplicationFiled: July 18, 2018Publication date: January 23, 2020Inventors: Hongwu Chen, Gui Fu, Zhenhua Hu, Zhike Zhang
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Patent number: 9305415Abstract: A banknote management system 1 includes a banknote handling apparatus 2 having stackers for stacking banknotes, the banknote handling apparatus sorting the banknotes based on sorting conditions set for the respective stackers, and sequentially stacking the sorted banknotes in the stackers corresponding to the sorting conditions; and a banknote management apparatus 3 managing the banknote handling apparatus. The system includes a DB registration specifying unit 32B specifying a stacker 11 a DB registration necessity of which is specified among the stackers; a banknote detailed information creating unit 37B creating banknote detailed information for recognizing a banknote that is stacked in the stacker a DB registration of which is set to be necessary; and a DB control unit 37D registering the banknote detailed information in a database 33. The system can minimize a memory capacity of the database and a volume of banknote detailed information to be registered in the database.Type: GrantFiled: September 22, 2008Date of Patent: April 5, 2016Assignee: GLORY LTD.Inventors: Gui Fu, Hajime Morino
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Patent number: 9270121Abstract: A control circuit for booting a number of devices in a certain order includes two delay circuits and three switch circuits, the first switch circuit and the first delay circuit receiving a power good signal and a voltage signal from a power supply unit and thus allowing a first device to boot and the first delay circuit outputting a first delay signal after a set time, to the second switch circuit and the second delay circuit, which repeat the process of the first delay circuit and switch circuit, to boot the remaining devices.Type: GrantFiled: May 31, 2013Date of Patent: February 23, 2016Assignee: ScienBiziP Consulting(Shenzhen)Co., Ltd.Inventors: Gui-Fu Xiao, Cheng-Fei Weng
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Patent number: 9158636Abstract: A serial advanced technology attachment dual in-line memory module (SATA DIMM) device includes a circuit board. A storage chip is arranged on the circuit board and stores a first firmware. A memory is arranged on the circuit board and stores a second firmware. A control chip is arranged on the circuit board and connected to the memory, to read the second firmware from the memory and load the second firmware in the storage chip when the first firmware stored in the storage chip is damaged. The control chip is also connected to the storage chip, to control the storage chip to read or to write data.Type: GrantFiled: October 24, 2013Date of Patent: October 13, 2015Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Gui-Fu Xiao, Peng Feng, Meng-Liang Yang
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Publication number: 20150103012Abstract: A keyboard includes a housing, a number of keys, a circuit board received in the housing, and a connecting port. The circuit board includes a main control unit, a key control unit, and an analyzing unit. The connecting port is configured for electrically connecting the circuit board to a main board of a computer. The main control unit includes a main controller. The key control unit includes a key controlling module electrically connected to the keys, and a processor electrically connected to the key controlling module through the main controller. The analyzing unit includes a display and an analyzing module. The analyzing module is electrically connected to the main controller and the connecting port, and is capable of reading breakdown information of the main board of the computer under the control of the main controller. The analyzing module displays the breakdown information on the display.Type: ApplicationFiled: February 11, 2014Publication date: April 16, 2015Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.Inventors: GUI-FU XIAO, CHENG-FEI WENG
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Publication number: 20150067223Abstract: A hot swappable memory motherboard includes a center processor unit and a memory unit. A button is set on the motherboard. Pressing the button, a signal is sent to the center processor unit to stop operating the memory unit.Type: ApplicationFiled: November 28, 2013Publication date: March 5, 2015Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: GUI-FU XIAO, CHENG-FEI WENG
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Publication number: 20150067388Abstract: A serial advanced technology attachment dual in-line memory module (SATA DIMM) device includes a circuit board. A storage chip is arranged on the circuit board and stores a first firmware. A memory is arranged on the circuit board and stores a second firmware. A control chip is arranged on the circuit board and connected to the memory, to read the second firmware from the memory and load the second firmware in the storage chip when the first firmware stored in the storage chip is damaged. The control chip is also connected to the storage chip, to control the storage chip to read or to write data.Type: ApplicationFiled: October 24, 2013Publication date: March 5, 2015Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: GUI-FU XIAO, PENG FENG, MENG-LIANG YANG
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Publication number: 20150058516Abstract: A motherboard includes a connector, an identification module, a Serial Advanced Technology Attachment (SATA) signal module, a Universal Serial Bus (USB) signal module, and a selection module. The connector is used to determine compatibility and connect a SATA-type external device with a SATA connector and a USB-type external device with a USB connector. The identification module is coupled to the connector. The identification module outputs a first signal when the connector is coupled to the SATA-type external device and outputs a second signal when the connector is coupled to the USB-type external device. The selection module connects either the SATA signal module or the USB signal module to the connector as appropriate.Type: ApplicationFiled: August 25, 2014Publication date: February 26, 2015Inventors: GUI-FU XIAO, CHENG-FEI WENG
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Publication number: 20150043296Abstract: When a measured current of a resistor is less than a preset current value after a device is inserted into a memory slot, a control chip and a storage chip does not receive voltages. When the measured current is not less than the preset current value and a count time reaches a preset time value, the control chip and the storage chip receive voltages, to read or write data. When measured current of the resistor is not less than the preset current value after the device is removed from the memory slot, the control chip and the storage chip receive voltages, to backup data. When the measured current is less than the preset current value and the count time reaches the preset time value, the control chip and the storage chip do not receive voltages.Type: ApplicationFiled: October 24, 2013Publication date: February 12, 2015Applicants: HON HAI PRECISION INDUSTRY CO., LTD., Hong Fu Jin Precision Industry (ShenZhen) Co., LtdInventors: GUI-FU XIAO, CHENG-FEI WENG
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Patent number: 8942057Abstract: When a measured current of a resistor is less than a preset current value after a device is inserted into a memory slot, a control chip and a storage chip does not receive voltages. When the measured current is not less than the preset current value and a count time reaches a preset time value, the control chip and the storage chip receive voltages, to read or write data. When measured current of the resistor is not less than the preset current value after the device is removed from the memory slot, the control chip and the storage chip receive voltages, to backup data. When the measured current is less than the preset current value and the count time reaches the preset time value, the control chip and the storage chip do not receive voltages.Type: GrantFiled: October 24, 2013Date of Patent: January 27, 2015Assignee: ScienBiziP Consulting (Shenzhen) Co., Ltd.Inventors: Gui-Fu Xiao, Cheng-Fei Weng
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Publication number: 20140219643Abstract: A heat gun head includes a housing. The housing defines two rows of outlets in a front end surface of the housing. When the heat gun head operates, hot air in the housing flows out of the housing through the two rows of outlets.Type: ApplicationFiled: April 24, 2013Publication date: August 7, 2014Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.Inventors: SONG MA, WU ZHOU, GUI-FU XIAO, WEI PANG
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Publication number: 20140206214Abstract: A power plug includes a main body and a rotating member rotatably connected to the main body. The rotating member includes a levering portion at a side of the point of rotation of the main body. The rotating member is rotated, to lever the power plug out of a power socket.Type: ApplicationFiled: March 14, 2013Publication date: July 24, 2014Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.Inventors: GUI-FU XIAO, LI-REN FU
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Publication number: 20140185250Abstract: A motherboard includes an interface and a switch module. The interface includes first to eighth pins used to connect a component object model (COM) connector or a registered jack 45 (RJ45) connector. The switch module is connected to the interface. The switch module is also connected to a serial communication bus and an Ethernet bus on the motherboard. The switch module is used to determine the type of a connector connected to the interface, and connect the connector to the serial communication bus or the Ethernet bus according to the determination.Type: ApplicationFiled: August 28, 2013Publication date: July 3, 2014Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.Inventors: GUI-FU XIAO, WEI PANG, CHENG-FEI WENG
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Patent number: 8767393Abstract: A draining apparatus for a keyboard of an electronic device includes a base for slantingly supporting the keyboard and a protecting film to be covered on the keyboard. The protecting film includes a waterproof sheet and a flange protruding up from edges of the waterproof sheet. The flange defines an outfall adjacent to a bottom end of the flange. In case liquid is spilled on the protecting film, the water may flow downward and islet out through the outfall.Type: GrantFiled: November 23, 2012Date of Patent: July 1, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Gui-Fu Xiao, Yang Liu, Cheng-Fei Weng
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Publication number: 20140167510Abstract: A control circuit for booting a number of devices in a certain order includes two delay circuits and three switch circuits, the first switch circuit and the first delay circuit receiving a power good signal and a voltage signal from a power supply unit and thus allowing a first device to boot and the first delay circuit outputting a first delay signal after a set time, to the second switch circuit and the second delay circuit, which repeat the process of the first delay circuit and switch circuit, to boot the remaining devices.Type: ApplicationFiled: May 31, 2013Publication date: June 19, 2014Inventors: GUI-FU XIAO, CHENG-FEI WENG