Abstract: A switched input circuit structure of the type which includes an input terminal receiving an input voltage and an output terminal connected to an input capacitor. An operational amplifier is included having a non-inverting terminal connected to a ground reference terminal, an inverting input terminal, and an output terminal feedback connected to the inverting input terminal and held in a virtual ground condition by a parallel of first and second charge paths which are connected between the input terminal of the switched input circuit structure and the inverting input terminal of the operational amplifier and connected to the supply voltage reference and the ground reference, respectively.

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract: A self-configurable, dual bridge, power amplifier has a window comparator sensing the level of input signals fed to the amplifier which-drives a plurality of configuring switches capable of configuring the amplifier as a single bridge amplifier driving a first and a second loads connected in series or as two distinct bridge amplifiers each driving one of the two loads. As long as the two levels of the input signals remain comprised between a range defined by a negative voltage reference and a positive voltage reference, the amplifier is configured as a single bridge driving the two loads in series, thus reducing sensibly power dissipation. Several embodiments of the configuring means are shown.

Abstract: A self-configurable, dual bridge, power amplifier has a window comparator to sense amplifier signals and control a plurality of configuring switches capable of configuring the amplifier either as a single bridge amplifier driving two loads connected in series or as two distinct bridge amplifiers each driving one of the two loads. When the two amplifier signals remain within a range defined by a negative voltage reference and a positive voltage reference, the amplifier is configured as a single bridge driving the two loads in series, thus reducing power dissipation. Several embodiments of the invention are shown.

Abstract: A device including a MOS power transistor, and a temperature sensor including a bipolar transistor integrated in the MOS transistor and having its emitter and collector connected directly to the source and gate terminals respectively of the MOS transistor. Parallel to the base-emitter junction of the bipolar transistor, there is connected a voltage source for biasing the junction to such a value that the bipolar transistor remains off at room temperature, and absorbs the maximum current supplied by a drive circuit of the MOS transistor at the maximum permissible temperature TUM. At temperature TUM, the bipolar transistor takes over control of the gate-source voltage of the MOS transistor for maintaining thermal feedback of the device at maximum temperature TUM.

Abstract: A self-configurable, dual bridge, power amplifier has a window comparator sensing the level of input signals fed to the amplifier which drives a plurality of configuring switches capable of configuring the amplifier as a single bridge amplifier driving a first and a second loads connected in series or as two distinct bridge amplifiers each driving one of the two loads. As long as the two levels of the input signals remain comprised between a range defined by a negative voltage reference and a positive voltage reference, the amplifier is configured as a single bridge driving the two loads in series, thus reducing sensibly power dissipation.

Abstract: Unitary-gain final stage particularly for monolithically integratable power amplifiers, which comprises a pair of final N-channel MOS power transistors. The first transistor has its drain terminal connected to a supply voltage and its source terminal connected to the drain terminal of the second transistor. The source terminal of the second transistor is connected to the ground. The output terminal of the power amplifier is connected between the source terminal of the first transistor and the drain terminal of the second transistor. The final stage furthermore comprises a high-gain feedback differential amplifier which has its non-inverting input terminal connected to the input of the power amplifier, its inverting input terminal connected to the output terminal of the differential amplifier and its output terminal connected to the gate terminal of the second transistor. A leveling circuit is furthermore connected to the gate terminal of the second transistor.

Abstract: The amplifier comprises a first and a second amplifier block of opposite phase driven by a single input signal and having its outputs connected to the two terminals of a load. It also comprises circuit means to disable one of the said amplifier blocks when the absolute value of the input signal is less than a predetermined threshold level. A passive feedback system capable of maintaining the amplifier gain constant is located between the aforesaid terminals of the load and the inputs to the two amplifier blocks.