Abstract: Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Abstract: The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

Abstract: In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a cock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tall node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes Is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.

Abstract: Circuitry for voltage-to-current conversion, and in particular to differential voltage-to-current conversion circuitry. Such circuitry is operable to receive a differential voltage input signal and output a corresponding differential current signal. First and second controllable current sinks are connected to first and second load nodes of the circuitry so as to draw corresponding sink currents from those nodes.

Abstract: In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a clock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tail node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.

Abstract: The present invention relates to circuitry for voltage-to-current conversion, and in particular to differential voltage-to-current conversion circuitry. Such circuitry is operable to receive a differential voltage input signal and output a corresponding differential current signal.

Abstract: Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Abstract: The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.