Patents by Inventor Guido Koerner

Guido Koerner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation
    Patent number: 8507351
    Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Anthony Mowry, Markus Lenski, Guido Koerner, Ralf Otterbach
  • DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
    Publication number: 20110230039
    Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 22, 2011
    Inventors: Anthony Mowry, Markus Lenski, Guido Koerner, Ralf Otterbach
  • Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation
    Patent number: 7977179
    Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: July 12, 2011
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Anthony Mowry, Markus Lenski, Guido Koerner, Ralf Otterbach
  • DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
    Publication number: 20090108295
    Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
    Type: Application
    Filed: April 24, 2008
    Publication date: April 30, 2009
    Inventors: Anthony Mowry, Markus Lenski, Guido Koerner, Ralf Otterbach
  • Method of forming an epitaxial layer for raised drain and source regions by removing contaminations
    Patent number: 7307026
    Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: December 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christof Streck, Guido Koerner, Thorsten Kammler
  • Method of forming an epitaxial layer for raised drain and source regions by removing contaminations
    Publication number: 20050026367
    Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.
    Type: Application
    Filed: February 25, 2004
    Publication date: February 3, 2005
    Inventors: Christof Streck, Guido Koerner, Thorsten Kammler