Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: A non-volatile memory device includes a chip of semiconductor material. The chip includes a memory and control means for performing a programming operation, an erasing operation and a reading operation on the memory in response to corresponding external commands. The chip further includes testing means for performing at least one test process including the repetition of at least one of said operations by the control means, and a single access element for enabling the testing means.

Abstract: The programming method includes the following steps: sequentially receiving a plurality of data words; temporarily storing each data word after its reception; and simultaneously writing in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments an address counter and sends a “ready” signal. Upon reception of each new data word, the memory verifies whether the address associated thereto is in the same sector as the initial data word and whether n data words have already been stored. If the sector is different, blind-programming step is terminated and the verifying is carried out; if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array, updates the address counter, and then sends the “ready” signal.

Abstract: The programming method includes the following steps: sequentially receiving a plurality of data words; temporarily storing each data word after its reception; and simultaneously writing in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments an address counter and sends a “ready” signal. Upon reception of each new data word, the memory verifies whether the address associated thereto is in the same sector as the initial data word and whether n data words have already been stored. If the sector is different, blind-programming step is terminated and the verifying is carried out; if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array, updates the address counter, and then sends the “ready” signal.

Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.