Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

Abstract: Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.

Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

Abstract: Briefly, in accordance with one or more embodiments, a memory array comprises two or more volumes, the volumes comprising two or more dice, respectively. The volumes are connected in a daisy chain configuration such that an output of a first volume is coupled to an input of a next volume, and the dice are connected in a daisy chain configuration such that an output of a first die is coupled to an input of a next die within the volume. In such a configuration, a first die in a first volume is capable of being appointed as part of a second volume.