Patents by Inventor Guido Notermans

Guido Notermans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and a method of manufacture of a semiconductor device
    Patent number: 11984515
    Abstract: A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p? region. A first space charge region and a second space charge region are formed within the p? region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: May 14, 2024
    Assignee: Nexperia B.V.
    Inventors: Hans-Martin Ritter, Steffen Holland, Guido Notermans, Joachim Utzig, Vasantha Kumar Vaddagere Nagaraju
  • SEMICONDUCTOR DEVICE AND ESD PROTECTION DEVICE COMPRISING THE SAME
    Publication number: 20220310587
    Abstract: An electrostatic discharge protection device is provided. The present device relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device comprises a first structure, including: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region. The third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.
    Type: Application
    Filed: March 29, 2022
    Publication date: September 29, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Steffen HOLLAND, Hans-Martin RITTER, Guido NOTERMANS
  • SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE OF A SEMICONDUCTOR DEVICE
    Publication number: 20220045222
    Abstract: A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p? region. A first space charge region and a second space charge region are formed within the p? region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hans-Martin Ritter, Steffen Holland, Guido Notermans, Joachim Utzig, Vasantha Kumar Vaddagere Nagaraju