Abstract: The present disclosure provides a complementary phototransistor pixel unit, a sensing and computing array structure and an operation method thereof. The complementary phototransistor pixel unit includes: a first photoelectric field effect transistor, which is a photoelectric field effect transistor based on an ultra-thin body and buried oxide layer; and a second photoelectric field effect transistor, the second photoelectric field effect transistor is a photoelectric field effect transistor based on an ultra-thin body and buried oxide layer, each of the first photoelectric field effect transistor and the second photoelectric field effect transistor is four-end device and has a gate electrode G, a source electrode S, a drain electrode D, and a well base electrode B, and the source electrode S or drain electrode D of the first photoelectric field effect transistor is connected to the source electrode S or drain electrode D of the second photoelectric field effect transistor.

Abstract: The present disclosure provides an image sensing computing unit and its operating method, an image sensing computer and an electronic device. Among them, the image sensing computing unit includes a first photosensitive unit and a second photosensitive unit. The second photosensitive unit is connected in series with the first photosensitive unit. The changing direction of the first threshold voltage of the first photosensitive unit when receiving light is opposite to the changing direction of the second threshold voltage of the second photosensitive unit when receiving light, so as to implement an in-situ logical operation between light input signals.

Abstract: A deep neural network based on analog FLASH computing array, includes a number of computing arrays, a number of subtractors, a number of activation circuit units and a number of integral-recognition circuit units. The computing array includes a number of computing units, a number of word lines, a plurality number of bit lines and a number of source lines. Each of the computing units includes a FLASH cell. The gate electrodes of the FLASH cells in the same column are connected to the same word line. The source electrodes of the FLASH cells in the same column are connected to the same source line, and the drain electrodes of the FLASH cells in the same row are connected to the same bit line. Each of the subtractors includes a positive terminal, a negative terminal and an output terminal.