Abstract: A power on reset circuit includes a bias current generation module for generating a bias current, a power on reset module for generating a power on reset voltage signal, and a feedback latch module, which are electrically connected in sequence. The power on reset module includes two series switches capable of being turned on or off to adjust the bias current to further adjust the power on reset time. The feedback latch module is used for latching the power on reset voltage signal to restrain the jitter of the power voltage within the input voltage range VIL-VIH of inverters in the power on stage and to avoid jump of the signal. The feedback latch module comprises a feedback branch, which is formed by two NMOS transistors in series connection and achieves rapider and stable output of the power on reset voltage signal through feedback of the signal.

Abstract: A wireless charging receiver which includes a wireless receiving panel provided with a receiving coil, and an aligning detection module including a first magnetic sensor chip array and a first solenoid set, is disposed on the lower portion of an electric automobile. A wireless charging transmitter comprises a wireless transmitting panel provided with a transmitting coil, a matching detection module including a photosensitive chip array, a second magnetic sensor chip array and a second solenoid set, and a driving device used for driving the wireless transmitting panel to move, is disposed on the ground of a parking area. Magnetic sensor chips of the first magnetic sensor chip array and solenoids of the first solenoid set are disposed around the receiving coil. The wireless charging transmitter. The wireless transmitting panel is disposed on the driving device and is driven by the driving device to be moved and aligned.

Abstract: A wireless charging receiver which includes a wireless receiving panel provided with a receiving coil, and an aligning detection module including a first magnetic sensor chip array and a first solenoid set, is disposed on the lower portion of an electric automobile. A wireless charging transmitter comprises a wireless transmitting panel provided with a transmitting coil, a matching detection module including a photosensitive chip array, a second magnetic sensor chip array and a second solenoid set, and a driving device used for driving the wireless transmitting panel to move, is disposed on the ground of a parking area. Magnetic sensor chips of the first magnetic sensor chip array and solenoids of the first solenoid set are disposed around the receiving coil. The wireless charging transmitter. The wireless transmitting panel is disposed on the driving device and is driven by the driving device to be moved and aligned.

Abstract: A power on reset circuit includes a bias current generation module for generating a bias current, a power on reset module for generating a power on reset voltage signal, and a feedback latch module, which are electrically connected in sequence. The power on reset module includes two series switches capable of being turned on or off to adjust the bias current to further adjust the power on reset time. The feedback latch module is used for latching the power on reset voltage signal to restrain the jitter of the power voltage within the input voltage range VIL-VIH of inverters in the power on stage and to avoid jump of the signal. The feedback latch module comprises a feedback branch, which is formed by two NMOS transistors in series connection and achieves rapider and stable output of the power on reset voltage signal through feedback of the signal.

Abstract: A method of fabricating a four-junction solar cell includes: forming a first epitaxial structure comprising first and second subcells and a cover layer over a first substrate through a forward epitaxial growth, and forming a second epitaxial structure comprising third and fourth subcells over the second substrate; forming a groove and a metal bonding layer; forming a groove on the cover layer surface of the first epitaxial structure and the substrate back surface of the second epitaxial structure, and depositing a metal bonding layer in the groove; and bonding the first epitaxial structure and the second epitaxial structure; bonding the cover layer surface of the first epitaxial structure and the substrate back surface of the second epitaxial structure, ensuring that the metal bonding layers are aligned to each other to realize dual bonding between the metal bonding layers and between the semiconductors through high temperature and high pressure treatment.

Abstract: A four-junction quaternary compound solar cell and a method thereof are provided. Forming a first subcell (100) with a first band gap, a lattice constant matching with the substrate on an InP grown substrate, forming a second subcell (200) with a second band gap bigger than the first band gap, a lattice constant matching with the substrate on the first subcell, forming a graded buffer layer (600) with a third band gap bigger than the second band gap on the second subcell, forming a third subcell (300) with a fourth band gap bigger than the third band gap, a lattice constant smaller than the substrate on the graded buffer layer, forming a fourth subcell (400) with a fifth band gap bigger than the fourth band gap, a lattice constant matching with the third subcell on the third subcell, and then forming the required four-junction solar cell then by succeeding process including removing the grown substrate, bonding a support substrate, forming electrodes, evaporating an anti-reflect film and so on.

Abstract: A fabrication method for an inverted solar cell includes: (1) providing a growth substrate; (2) depositing a SiO2 mask layer over the surface of the growth substrate to form a patterned substrate; (3) forming a sacrificial layer with epitaxial growth over the patterned substrate, wherein the sacrificial layer encompasses the entire SiO2 mask pattern; (4) forming a buffer layer over the sacrificial layer via epitaxial growth; (5) forming a semiconductor material layer sequence of the inverted solar cell over the buffer layer with epitaxial growth; (6) bonding the semiconductor material layer sequence of the inverted solar cell with a supporting substrate; (7) selectively etching the SiO2 mask layer by wet etching; and (8) selectively etching the sacrificial layer by wet etching to lift off the growth substrate.

Abstract: A flip-chip solar cell chip includes a bonding transfer substrate; a metal bonding layer; a flip-chip solar cell epitaxial layer that bonds with the bonding transfer substrate with the metal bonding layer; the flip-chip solar cell epitaxial layer and the metal bonding layer are divided into two or more portions; the surface of the flip-chip solar cell epitaxial layer has a front electrode; and the metal bonding layer is connected with the ends of the front electrode to form a series connection of the divided epitaxial layer. Advantageously, the division of the solar cell epitaxial layer into a plurality of completely-separated portions greatly reduces photo currents and power loss of cell chip series resistance while realizing multiplied increase of output voltage, thereby improving photoelectric conversion efficiency. The use of metal bonding layer as the back electrode realizes extremely low resistance loss of the back electrode.

Abstract: A high-concentration solar cell includes an epitaxial layer structure, an upper patterned electrode on the top surface, and a back electrode on the back surface. The upper patterned electrode includes a primary pattern and a secondary pattern, where the primary pattern is composed of a series of small metal isosceles trapezoids around the perimeter of the cell. The narrower base of each metal trapezoid points toward an interior of the cell. A lead soldering pad is located within each metal trapezoid for being soldered to an external conductor for carrying the solar cell current. The secondary pattern consists of thin spaced conductors that connect to the angled sides and base of each trapezoid and spread current across the top surface of the cell. The current along the angled sides of each trapezoid is well-distributed to all the spaced conductors connected to the angled sides to avoid current crowding.

Abstract: A fabrication method for high-efficiency multi junction solar cells, including: providing a Ge substrate for semiconductor epitaxial growth; growing an emitter region over the Ge substrate (as the base) to form a first subcell with a first band gap; forming a second subcell with a second band gap larger than the first band gap and lattice matched with the first subcell over the first subcell via MBE; forming a third subcell with a third band gap larger than the second band gap and lattice matched with the first and second subcells over the second subcell via MOCVD; and forming a fourth subcell with a fourth band gap larger than the third band gap and lattice matched with the first, second and third subcells over the third subcell via MOCVD.

Abstract: A four-junction quaternary compound solar cell and a method thereof are provided.

Abstract: A fabrication method for an inverted solar cell includes: (1) providing a growth substrate; (2) depositing a SiO2 mask layer over the surface of the growth substrate to form a patterned substrate; (3) forming a sacrificial layer with epitaxial growth over the patterned substrate, wherein the sacrificial layer encompasses the entire SiO2 mask pattern; (4) forming a buffer layer over the sacrificial layer via epitaxial growth; (5) forming a semiconductor material layer sequence of the inverted solar cell over the buffer layer with epitaxial growth; (6) bonding the semiconductor material layer sequence of the inverted solar cell with a supporting substrate; (7) selectively etching the SiO2 mask layer by wet etching; and (8) selectively etching the sacrificial layer by wet etching to lift off the growth substrate.

Abstract: A high-efficiency four-junction solar cell includes: an InP growth substrate; a first subcell formed over the growth substrate, with a first band gap, and a lattice constant matched with that of the growth substrate; a second subcell formed over the first subcell, with a second band gap larger than the first band gap, and a lattice constant matched with that of the growth substrate; a third subcell formed over the second subcell, with a third band gap larger than the second band gap, and a lattice constant matched with that of the substrate lattice; a composition gradient layer formed over the third subcell, with a fourth band gap larger than the third band gap; and a fourth subcell formed over the composition gradient layer, with a fifth band gap larger than the third band gap, and a lattice constant mismatched with that of the substrate.

Abstract: A high-concentration solar cell includes an epitaxial layer structure, an upper patterned electrode on the top surface, and a back electrode on the back surface. The upper patterned electrode includes a primary pattern and a secondary pattern, where the primary pattern is composed of a series of small metal isosceles trapezoids around the perimeter of the cell. The narrower base of each metal trapezoid points toward an interior of the cell. A lead soldering pad is located within each metal trapezoid for being soldered to an external conductor for carrying the solar cell current. The secondary pattern consists of thin spaced conductors that connect to the angled sides and base of each trapezoid and spread current across the top surface of the cell. The current along the angled sides of each trapezoid is well-distributed to all the spaced conductors connected to the angled sides to avoid current crowding.

Abstract: A high-concentration multi-junction solar cell and method for fabricating same is provided. The high-concentration multi-junction solar cell comprises a top cell, an intermediate cell, a bottom cell and two tunneling junctions connecting the top cell and intermediate cell and the intermediate cell and bottom cell. The emitter layers of the top and intermediate cells both employ the graded doping concentrations and have high open circuit voltage and short circuit current. The top cell emitter layer is over several hundred nanometers thicker than that of the traditional multi-junction cell so as to decrease the whole series resistance of the multi-junction cell, improve the fill factor, and gain higher photoelectric conversion efficiency.