Patents by Inventor Guilherme Cox

Guilherme Cox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • UNIFIED VIRTUAL MEMORY MANAGEMENT IN HETEROGENEOUS COMPUTING SYSTEMS
    Publication number: 20230032278
    Abstract: Apparatuses, systems, and techniques for memory management are disclosed. In at least one embodiment, memory management is provided for a heterogenous system, for example, a system including a CPU and a GPU, in which redundant or unnecessary memory transfers are reduced.
    Type: Application
    Filed: July 19, 2022
    Publication date: February 2, 2023
    Inventors: Weixi Zhu, Guilherme Cox, Mark Hairgrove
  • Single instruction multiple data page table walk scheduling at input output memory management unit
    Patent number: 10437736
    Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 8, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arkaprava Basu, Eric Van Tassell, Mark Oskin, Guilherme Cox, Gabriel Loh
  • SINGLE INSTRUCTION MULTIPLE DATA PAGE TABLE WALK SCHEDULING AT INPUT OUTPUT MEMORY MANAGEMENT UNIT
    Publication number: 20190196978
    Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Arkaprava Basu, Eric Van Tassell, Mark Oskin, Guilherme Cox, Gabriel Loh