Abstract: An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality of condition code bits from a first register to a second register.

Abstract: Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region.

Abstract: Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region.

Abstract: An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality of condition code bits from a first register to a second register.

Abstract: Provided are a method, system, and program for parallelizing source code with a compiler. Source code including source code statements is received. The source code statements are processed to determine a dependency of the statements. Multiple groups of statements are determined from the determined dependency of the statements, wherein statements in one group are dependent on one another. At least one directive is inserted in the source code, wherein each directive is associated with one group of statements. Resulting threaded code is generated including the inserted at least one directive. The group of statements to which the directive in the resulting threaded code applies are processed as a separate task. Each group of statements designated by the directive to be processed as a separate task may be processed concurrently with respect to other groups of statements.