Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: A semiconductor includes a semiconductor substrate having first and second opposite facing surfaces. An amplifier device is formed in the semiconductor substrate, the amplifier device is configured to amplify an RF signal at a fundamental frequency. A first dielectric layer is formed on the first surface of the substrate. A first metallization layer is formed on the first dielectric layer. The first metallization layer is spaced apart from the substrate by the first dielectric layer. The first metallization layer includes a first elongated finger interdigitated with a first reference potential pad. The first elongated finger is physically disconnected from the first reference potential pad. The first reference potential pad includes a first patterned shape that is devoid of metallization. The first patterned shape has a geometry that filters harmonic components of the fundamental frequency.

Abstract: A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

Abstract: A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.