Patents by Inventor Guillaume E. A. Lousberg

Guillaume E. A. Lousberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit with interconnect test unit
    Patent number: 6807505
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: October 19, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Franciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg
  • Method and apparatus for testing a memory array using compressed responses
    Patent number: 6721911
    Abstract: A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: April 13, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Erik J. Marinissen, Guillaume E. A. Lousberg, Paul Wielage
  • Circuit with interconnect test unit
    Publication number: 20040059535
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Application
    Filed: July 16, 2003
    Publication date: March 25, 2004
    Inventors: Franciscus G.M. De Jong, Mathias N.M. Muris, Robertus M.W. Raaijmakers, Guillaume E.A. Lousberg
  • Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit
    Patent number: 6622108
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 16, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Franciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg
  • Clock domain test isolation
    Patent number: 6131173
    Abstract: The invention relates to an integrated circuit, comprising a number of independent clock domains. Seam circuits are provided in the interface signals paths between the clock domains in order to be able to isolate clock domains from each other during testing. Each seam circuit comprises a feedback loop having a multiplexer and a flip-flop feeding a first input of the multiplexer, a second input of the multiplexer being connected to the seam input, an output of the feedback loop being connected to the output; so that a first state of the multiplexer allows loading of a data bit in the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: October 10, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Johan C. Meirlevede, Gerardus A. A. Bos, Jacobus A. M. Jacobs, Guillaume E. A. Lousberg