Abstract: An electronic device has a plurality of subdevices with each subdevice coupled to a test interface. The test interfaces are arranged in a chain of test interfaces by coupling the TDO contact of a predecessor test interface to the TDI contact of a successor test interface in the chain. In addition, at its beginning, the chain is extended with a boundary scan compliant test interface for testing other parts of electronic device. Both the TDO contact of the last test interface in the chain as well as the TDO contact of test interface are coupled to a bypass multiplexer, thus yielding two possible routes from test data input to test data output: through the full chain or through test interface only. Consequently, electronic device can be tested or debugged as a macro device or as a collection of subdevices.

Abstract: An integrated circuit is switchable between a normal operating mode and a test mode. A functional circuit and a test pattern converter are both coupled between input contacts, output contacts and a redefinable contact of the integrated circuit. In the test mode respectively the test pattern converter drives the outputs contacts and, dependent on the circuit configuration, the redefinable contact. The test pattern converter is arranged to provide a first and second relation between signals at the input contacts and the output contacts, with the redefinable contact used as an input or output contact respectively, dependent on the circuit configuration. The relations have been selected so as to permit testing of stuck-at and cross-connect errors with the redefinable contact used as input and output contact respectively.

Abstract: A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.

Abstract: An electronic device (100) has a plurality of subdevices (120a, 120b) with each subdevice (120a; 120b) coupled to a test interface (140a; 140b). The test interfaces (140a, 140b) are arranged in a chain of test interfaces (140) by coupling the TDO contact (142b) of a predecessor test interface (140a) to the TDI contact (141b) of a successor test interface (140b) in the chain (140). In addition, at its beginning, the chain (140) is extended with a boundary scan compliant test interface (160) for testing other parts of electronic device (100). Both the TDO contact (142b) of the last test interface (140b) in the chain (140) as well as the TDO contact (162) of test interface (160) are coupled to a bypass multiplexer (102), thus yielding two possible routes from test data input (110) to test data output (112): through the full chain (140, 160) or through test interface (160) only. Consequently, electronic device (100) can be tested or debugged as a macro device or as a collection of subdevices (120a, 120b).

Abstract: An integrated circuit is switchable between a normal operating mode and a test mode. A functional circuit and a test pattern converter are both coupled between input contacts, output contacts and a redefinable contact of the integrated circuit. In the test mode respectively the test pattern converter drives the outputs contacts and, dependent on the circuit configuration, the redefinable contact. The test pattern converter is arranged to provide a first and second relation between signals at the input contacts and the output contacts, with the redefinable contact used as an input or output contact respectively, dependent on the circuit configuration. The relations have been selected so as to permit testing of stuck-at and cross-connect errors with the redefinable contact used as input and output contact respectively.