Abstract: A method and system for performing a duty cycle correction and quadrature error correction for a quarter-rate architecture TX/RX communication system, including correcting a duty cycle error between a first clock signal and a second clock signal, and correcting a quadrature error between a third clock signal and a fourth clock signal.

Abstract: Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.

Abstract: The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path. Embodiments also include at least one switch and at least one capacitor located between a source and a drain of at least one of the first transistor and the second transistor to create a capacitive path between the source and drain, wherein the at least one switch and at least one capacitor are configured to reduce bandwidth.

Abstract: Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.

Abstract: Various embodiments provide for data sampling with loop-unrolled decision feedback equalization. In particular, some embodiments provide for an unrolled first-tap Decision Feedback Equalizer (DFE) loop that comprises parallel data samplers that each include a tri-state output.

Abstract: The present disclosure relates to an apparatus and method for correcting a duty cycle of at least one signal. The apparatus may comprise at least one set of inverters configured to receive the at least one signal and correct the duty cycle of the at least one signal at a correction location of a plurality of correction locations based upon, at least in part, a transmission rate mode of a plurality of transmission rate modes.

Abstract: Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal.

Abstract: A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.

Abstract: A system, method, and circuits for processing a boundary scan result involve receiving the boundary scan result as input data to a comparator, and performing a comparison based on the input data and a selected reference level to form a comparison result. A capture device that stores the comparison result is set, reset or write enabled based on the comparison result and a reference value indicating which of two reference levels is the selected reference level. Additionally, a determination is made whether to change the selected reference level for a subsequent comparison based on the comparison result, the reference value, and the output of the capture device.

Abstract: A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one of the resistors, thereby calibrating the impedance cell. The output impedance can be set by identifying a combination of calibrated impedance cells that need to be activated in order to produce the target output impedance.

Abstract: A system, method, and circuits for power efficient margining in a differential output driver that includes segments connected to outputs of the driver. Each segment can be configured independently to different states by activating corresponding transistor combinations. In a transmitting state, the transistors transmit data by establishing current paths between the driver outputs and a positive supply rail or a ground rail. In a margining state, the transistors are statically configured to form current paths that differ from those of the transmitting state, such that the segment contributes substantially a same differential impedance between the driver outputs as would be contributed by the segment when in the transmitting state, while contributing a different common mode impedance than in the transmitting state. The current paths of the margining state extend through transistors that transmit data in the transmitting state.

Abstract: A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Abstract: Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.

Abstract: A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Abstract: Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.

Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.

Abstract: Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces operate at different voltage levels than modern CMOS integrated circuits and conventional circuits to interface with these other signaling interfaces exhibit relatively high power consumption. In the context of a transmitter with a P-type substrate, an output driver is embodied in a deep N-well with retrograde P-wells and is biased with voltage biases that can float with respect to the VDD and VSS supplies provided to the CMOS integrated circuit. In the context of a receiver with a P-type substrate, a portion of a receiver is embodied in a deep N-well and biased with floating voltage biases such that the receiver is compatible with signaling received from a signaling technology with disparate voltage levels.

Abstract: Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.

Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.

Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.