Patents by Inventor Guillaume SCHON
Guillaume SCHON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10902113Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.Type: GrantFiled: October 25, 2017Date of Patent: January 26, 2021Assignee: ARM LimitedInventors: Guillaume Schon, Frederic Jean Denis Arsanto, Carlo Dario Fanara, Jocelyn François Orion Jaubert
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Patent number: 10572262Abstract: An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.Type: GrantFiled: July 17, 2017Date of Patent: February 25, 2020Assignee: ARM LimitedInventors: Jocelyn Francois Orion Jaubert, Frederic Jean Denis Arsanto, Guillaume Schon, Carlo Dario Fanara
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Patent number: 10540299Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.Type: GrantFiled: June 30, 2017Date of Patent: January 21, 2020Assignee: ARM LimitedInventors: Carlo Dario Fanara, Frederic Jean Denis Arsanto, Guillaume Schon, Jocelyn Francois Orion Jaubert
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Patent number: 10445500Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.Type: GrantFiled: June 28, 2017Date of Patent: October 15, 2019Assignee: ARM LimitedInventors: Guillaume Schon, Frederic Jean Denis Arsanto, Jocelyn François Orion Jaubert, Carlo Dario Fanara
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Publication number: 20190121967Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Guillaume SCHON, Frederic Jean Denis ARSANTO, Carlo Dario FANARA, Jocelyn François Orion JAUBERT
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Publication number: 20190018686Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Jocelyn Francois Orion JAUBERT, Frederic Jean Denis ARSANTO, Guillaume SCHON, Carlo Dario FANARA
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Publication number: 20190005240Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Guillaume SCHON, Frederic Jean Denis ARSANTO, Jocelyn François Orion JAUBERT, Carlo Dario FANARA
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Publication number: 20190004977Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Carlo Dario FANARA, Frederic Jean Denis ARSANTO, Guillaume SCHON, Jocelyn Francois Orion JAUBERT
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Patent number: 9424045Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.Type: GrantFiled: January 29, 2013Date of Patent: August 23, 2016Assignee: ARM LimitedInventors: Cedric Denis Robert Airaud, Luca Scalabrino, Frederic Jean Denis Arsanto, Guillaume Schon, Frederic Claude Marie Piry, Albin Pierick Tonnerre
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Patent number: 9400655Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.Type: GrantFiled: March 20, 2013Date of Patent: July 26, 2016Assignee: ARM LimitedInventors: Guillaume Schon, Cedric Denis Robert Airaud, Frederic Jean Denis Arsanto, Luca Scalabrino
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Patent number: 9361111Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.Type: GrantFiled: January 9, 2013Date of Patent: June 7, 2016Assignee: ARM LimitedInventors: Luca Scalabrino, Melanie Emanuelle Lucie Teyssier, Cedric Denis Robert Airaud, Guillaume Schon
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Patent number: 9311087Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.Type: GrantFiled: December 21, 2012Date of Patent: April 12, 2016Assignee: ARM LimitedInventors: Luca Scalabrino, Cédric Denis Robert Airaud, Guillaume Schon, Frederic Jean Denis Arsanto
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Patent number: 9286069Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier.Type: GrantFiled: December 21, 2012Date of Patent: March 15, 2016Assignee: ARM LimitedInventors: Cédric Denis Robert Airaud, Luca Scalabrino, Frederic Jean Denis Arsanto, Guillaume Schon
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Patent number: 9075621Abstract: A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.Type: GrantFiled: December 23, 2011Date of Patent: July 7, 2015Assignee: ARM LimitedInventors: Guillaume Schon, Mélanie Emanuelle Lucie Teyssier, Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
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Patent number: 9052909Abstract: A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.Type: GrantFiled: December 7, 2011Date of Patent: June 9, 2015Assignee: ARM LimitedInventors: Frederic Claude Marie Piry, Luca Scalabrino, Guillaume Schon, Melanie Emanuelle Lucie Teyssier
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Publication number: 20140289501Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.Type: ApplicationFiled: March 20, 2013Publication date: September 25, 2014Inventors: Guillaume SCHON, Cedric Denis Robert AIRAUD, Frederic Jean Denis ARSANTO, Luca SCALABRINO
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Publication number: 20140215189Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Applicant: ARM LIMITEDInventors: Cedric Denis Robert AIRAUD, Luca SCALABRINO, Frederic Jean Denis ARSANTO, Guillaume SCHON, Frederic Claude Marie PIRY, Albin Pierick TONNERRE
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Publication number: 20140195787Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: ARM LIMITEDInventors: Luca SCALABRINO, Melanie Emanuelle Lucie TEYSSIER, Cedric Denis Robert AIRAUD, Guillaume SCHON
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Publication number: 20140181485Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ARM LIMITEDInventors: Luca SCALABRINO, Cédric Denis Robert Airaud, Guillaume Schon, Frederic Jean Denis Arsanto
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Publication number: 20140181478Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ARM LimitedInventors: Cédric Denis Robert AIRAUD, Luca Scalabrino, Frederic Jean Denis Arsanto, Guillaume Schon