Abstract: A circuit for compacting variable length data words into a fixed word length format is disclosed. Each variable length data word and its associated leading 0's are separated by a delimiter bit and stored in memory. When the memory is accessed, the output word is loaded in parallel into a first shift register and shifted to strip the leading 0's and delimiter bit. The remaining data bits are then shifted serially into a second shift register. When the second shift register is full, the resultant fixed length data word is latched out. When the first shift register is empty, the next word is loaded in from memory. In this way, a series of variable length words may be compacted into a series of fixed length words. This circuit is useful for compacting variable length Huffman codes since the boundaries between codes are self evident. This circuit can also be used as a character generator, where the variable length data output comprises the bits required to generate a character image on a raster scanned display.

Abstract: Apparatus for maintaining constant tension on a web during movement thereof, e.g., during positioning original documents in an exposure station of a reproduction machine. The web is coupled between a take up reel and a supply reel, with each reel being driven by an electric motor. The two motors are energized by a signal from the same source, except that the signal applied to the supply reel motor is the derivative of that applied to the take up reel motor. In such manner, the supply reel is energized during periods of acceleration or deceleration of the web thereby maintaining constant tension on the web during positioning.