Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.

Abstract: One embodiment of the invention provides a system that facilitates integrating a simulation log into a verification environment. The system operates by first creating the simulation log during a simulation of a register transfer language description of an integrated circuit design. Next, for each entry in the simulation log, the system places a corresponding entry in a “log entry table.” When a user selects an entry from the simulation log, the system determines a file offset for the entry within the simulation log. Next, the system locates the corresponding entry in the log entry table. The system then uses the log entry table to locate entries within simulator state files, which describe which portion of the integrated circuit is being simulated. This enables the system to display the corresponding entries from the simulator state files to a user.

Abstract: One embodiment of the invention provides a system that facilitates integrating a simulation log into a verification environment. The system operates by first creating the simulation log during a simulation of a register transfer language description of an integrated circuit design. Next, for each entry in the simulation log, the system places a corresponding entry in a “log entry table.” When a user selects an entry from the simulation log, the system determines a file offset for the entry within the simulation log. Next, the system locates the corresponding entry in the log entry table. The system then uses the log entry table to locate entries within simulator state files, which describe which portion of the integrated circuit is being simulated. This enables the system to display the corresponding entries from the simulator state files to a user.

Abstract: During simulation of an IC design, traces of certain signals can be generated, thereby allowing defects in the design to be detected. The traces of these signals, i.e. the target set, are typically saved in a value change file. Unfortunately, this value change file can get very large, thereby causing capacity and performance problems. A technique is described in which a subset of signals that can regenerate the target set of signals is determined. Determining the subset of signals can include identifying state elements (e.g. edge-triggered devices) and corresponding signal dependencies of the IC design. Advantageously, only this subset of signals needs to be saved in the value change file, thereby significantly reducing its size. The target set of signals can be computed on demand after reading the value change file.

Abstract: A method for handling an application in a communication between a first end and a second end involving an application layer, a transport layer, and a network layer, which method includes steps of: (a) receiving network layer packets from the first end of the communication, which packets contain application information provided using application layer processing; (b) processing the application information using application layer processing; and (c) transmitting network layer packets toward the second end of the communication, which packets contain information resulting from the application layer processing.

Abstract: Embodiments of the present invention provide method and apparatus that encrypt/decrypt messages sent over a network rapidly, and which do not require large amounts of computational or memory resources. In particular, one embodiment of the present invention is a method of providing security in a communication between a first end and a second end involving a security layer and a transport layer, wherein at some security layer messages sent from the first end are long security layer messages, which method includes steps of: (a) identifying a long security layer message in a transport layer segment received from the first end, decrypting security layer information contained in the transport layer segment, and buffering decrypted security layer information; (b) identifying the end of the long security layer message, and verifying the long security message; and (c) sending the decrypted long security layer message to the second end.

Abstract: A mechanism for implementing a store instruction so that a single cache access stage is required. Since a load instruction requires a single cache access stage, in which a cache read occur, both the store and load instructions of the present invention utilize a uniform number of cache access stages. The store instruction is implemented in a pipeline microprocessor such that during the pipeline stages of a given store instruction, the cache memory is read and there is an immediate determination if there is a tag hit for the store. Assuming there is cache hit, the cache write associated with the given store instruction is implemented during the same pipeline stage as the cache access stage of a subsequent instruction that does not write to the cache or if there is no instruction. For example, a cache data write occurs for the given store simultaneously with the cache tag read of a subsequent store instruction. This allows for a more uniform and efficient pipeline format for each instruction.

Abstract: A computer system for generating a summary of test coverage for a hardware description. The hardware description corresponds to a finite state machine (FSM). This embodiment requires at least one test vector. The computer system comprises a memory and a processor. The memory is for storing the hardware description and the test vector. The processor, coupled to the memory, uses the hardware description and generates state information corresponding to the FSM. The processor, using the state information, further generates a first description. The first description includes a description for monitoring states and signals in the hardware description. The processor, using the test vector, the hardware description and the first description, further generates the test coverage summary.