Patents by Inventor Guillermo R. Maturana

Guillermo R. Maturana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10372856
    Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 6, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Ngai Ngai William Hung, Qiang Qiang, Guillermo R. Maturana, Jasvinder Singh, Dhiraj Goswami
  • Publication number: 20160034624
    Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Applicant: SYNOPSYS, INC.
    Inventors: Ngai Ngai William Hung, Qiang Qiang, Guillermo R. Maturana, Jasvinder Singh, Dhiraj Goswami
  • Patent number: 9195634
    Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: November 24, 2015
    Assignee: SYNOPSYS, INC.
    Inventors: Ngai Ngai William Hung, Qiang Qiang, Guillermo R. Maturana, Jasvinder Singh, Dhiraj Goswami
  • Patent number: 8650513
    Abstract: Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 11, 2014
    Assignee: Synopsys, Inc.
    Inventors: Arturo Salz, Guillermo R. Maturana, In-Ho Moon, Lisa R. McIlwain
  • Publication number: 20120136635
    Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.
    Type: Application
    Filed: December 14, 2010
    Publication date: May 31, 2012
    Applicant: SYNOPSYS, INC.
    Inventors: Ngai Ngai William Hung, Qiang Qiang, Guillermo R. Maturana, Jasvinder Singh, Dhiraj Goswami
  • Patent number: 8150787
    Abstract: One embodiment of the present invention provides a system that reuses information associated with a constraint solving operation for a problem domain. This system begins by receiving a constraint problem from the problem domain. Then, the system searches through a problem cache for an entry which corresponds to the canonical representation. If a corresponding entry does not exist in the problem cache, the system produces an entry in the problem cache for the canonical representation. Otherwise, if a corresponding entry already exists in the problem cache, the system generates a solution to the canonical representation by reusing the solver heuristic associated with the corresponding entry in the problem cache.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: April 3, 2012
    Assignee: Synopsys, Inc.
    Inventor: Guillermo R. Maturana
  • Publication number: 20120072876
    Abstract: Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.
    Type: Application
    Filed: June 30, 2011
    Publication date: March 22, 2012
    Applicant: SYNOPSYS, INC.
    Inventors: Arturo Salz, Guillermo R. Maturana, In-Ho Moon, Lisa R. Mcllwain
  • Publication number: 20100017352
    Abstract: One embodiment of the present invention provides a system that reuses information associated with a constraint solving operation for a problem domain. This system begins by receiving a constraint problem from the problem domain. Then, the system searches through a problem cache for an entry which corresponds to the canonical representation. If a corresponding entry does not exist in the problem cache, the system produces an entry in the problem cache for the canonical representation. Otherwise, if a corresponding entry already exists in the problem cache, the system generates a solution to the canonical representation by reusing the solver heuristic associated with the corresponding entry in the problem cache.
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Applicant: SYNOPSYS, INC.
    Inventor: Guillermo R. Maturana