Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.

Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.

Abstract: Embodiments of the present invention enable mobile devices to behave as a dedicate remote control for different target devices through camera detection of a particular target device and autonomous execution of applications linked to the detected target device. Also, when identical target devices are detected, embodiments of the present invention may be configured to use visual identifiers and/or positional data associated with the target device for purposes of distinguishing the target device of interest. Additionally, embodiments of the present invention are capable of being placed in a surveillance mode in which camera detection procedures are constantly performed to locate target devices. Embodiments of the present invention may also enable users to engage this surveillance mode by pressing a button located on the mobile device. Furthermore, embodiments of the present invention may be trained to recognize target devices.

Abstract: Embodiments of the present invention are capable of determining a face direction associated with a detected subject (or multiple detected subjects) of interest within a 3D space using face detection procedures, while simultaneously avoiding the pick up of other environmental sounds. In addition, if more than one face is detected, embodiments of the present invention can automatically detect an active speaker based on the recognition of facial movements consistent with the performance of providing audio (e.g., tracking mouth movements) by those subjects whose faces were detected. Once determinations are made regarding face direction of the detected subject, embodiments of the present invention may dynamically adjust the audio acquisition capabilities of the audio capture device (e.g., microphone devices) relative to the location of the detected subject using beamforming techniques for instance.

Abstract: A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.

Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.

Abstract: A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: Briefly, a processor and a method of estimating an active energy consumption of two or more cores of a processor based on dispatching micro operations to one or more execution units of the processor.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. In an embodiment, a load operation may be predicted to not conflict with older pending store operations if a saturation counter corresponding to the load operation is below a threshold value and a maximum rate of mispredictions has not occurred. Other embodiments are also disclosed.

Abstract: Devices, systems, and methods may perform micro-operation processing with data validity tracking to determine fast or slow mode processing at a reservation station. A method includes determining whether a condition related to validity of data in a reorder buffer of an out-of-order subsystem of a processor core is met, based on a criterion other than a valid data indication from said reorder buffer. In one embodiment, in a fast mode a reservation station may dispatch micro-operations to execution and in a slow mode the reservation station may wait for a valid indication from the reorder buffer prior to dispatching the micro-operation.

Abstract: Briefly, a processor and a method of estimating an active energy consumption of two or more cores of a processor based on dispatching micro operations to one or more execution units of the processor.

Abstract: A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: Devices, systems and methods of tracking data validity. For example, a method includes determining whether a condition related to validity of data in a reorder buffer of an out-of-order subsystem of a processor core is met, based on a criterion other than a valid data indication from said reorder buffer.

Abstract: Some embodiments of the invention provide devices, systems and methods of handling FXCH instructions data validity. For example, an apparatus in accordance with an embodiment of the invention includes a real register file unit able to perform a floating point exchange micro-instruction, by modifying an operand of a floating point micro-instruction that attempts to access a floating point register of said real register file unit, if said operand requires modification based on the floating point exchange micro-instruction.

Abstract: Embodiments of the invention provide a method that includes partitioning a series of instructions of a trace into a plurality of dependency sets before executing the trace; and marking a first group of the dependency sets as critical and a second group of the dependency sets as non-critical Embodiments of the invention also provide a method that may identify a dependency set in the second group, which delays the execution of at least one dependency set in the first group, as a delaying dependency set; counting the number of delays caused by the delaying dependency set; and re-marking the delaying dependency set as critical when a predefined delaying event threshold is reached.