Abstract: A mass storage memory device is disclosed. The device includes a nonvolatile memory, a volatile memory configured to store logical to physical (L2P) data associating logical addresses of data stored in the nonvolatile memory with physical locations of the nonvolatile memory at which the data is stored, and a controller. The controller writes L2P data in the nonvolatile memory so the L2P data can be preserved through a power failure. The controller also writes L2P data stored in the nonvolatile memory to the volatile memory to rebuild the L2P table.

Abstract: A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data.

Abstract: Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.

Abstract: A mass storage memory device is disclosed. The device includes a nonvolatile memory, a volatile memory configured to store logical to physical (L2P) data associating logical addresses of data stored in the nonvolatile memory with physical locations of the nonvolatile memory at which the data is stored, and a controller. The controller writes L2P data in the nonvolatile memory so the L2P data can be preserved through a power failure. The controller also writes L2P data stored in the nonvolatile memory to the volatile memory to rebuild the L2P table.

Abstract: A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data.

Abstract: Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.

Abstract: Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.