Abstract: Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line.

Abstract: A non-volatile storage system includes non-volatile storage elements and one or more managing circuits in communication with the non-volatile storage elements. The non-volatile storage elements are arranged in blocks including a first block reserved for system use and a second block. The first block stores a pre-determined data pattern that was written to the first block subsequent to system testing and prior to completion of manufacturing of the non-volatile storage system. Subsequent to completion of manufacturing of the non-volatile storage system, the one or more managing circuits sense information stored in the first block and determine an error metric for the sensed information with respect to the pre-determined data pattern. The one or more managing circuits determine that the system experienced an IR reflow process if the error metric was determined to satisfy the threshold.

Abstract: Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.

Abstract: Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line.

Abstract: A non-volatile storage system includes non-volatile storage elements and one or more managing circuits in communication with the non-volatile storage elements. The non-volatile storage elements are arranged in blocks including a first block reserved for system use and a second block. The first block stores a pre-determined data pattern that was written to the first block subsequent to system testing and prior to completion of manufacturing of the non-volatile storage system. Subsequent to completion of manufacturing of the non-volatile storage system, the one or more managing circuits sense information stored in the first block and determine an error metric for the sensed information with respect to the pre-determined data pattern. The one or more managing circuits determine that the system experienced an IR reflow process if the error metric was determined to satisfy the threshold.

Abstract: A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value.

Abstract: Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: Systems and methods are disclosed for reducing programming interference in solid-state memory using a program suspend command. A data storage system includes a non-volatile memory array including a plurality of non-volatile memory devices and a controller configured to partially program a first cell coupled to a first word line. When a programming criterion associated with the first cell is met, the controller executes a program suspend command after which a second cell coupled to the first word line is at least partially programmed. Programming of the first cell is resumed following said at least partial programming of the second cell.

Abstract: Systems and methods are disclosed for reducing programming interference in solid-state memory using a program suspend command. A data storage system includes a non-volatile memory array including a plurality of non-volatile memory devices and a controller configured to partially program a first cell coupled to a first word line. When a programming criterion associated with the first cell is met, the controller executes a program suspend command after which a second cell coupled to the first word line is at least partially programmed. Programming of the first cell is resumed following said at least partial programming of the second cell.

Abstract: A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment. the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment, the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.

Abstract: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.

Abstract: A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

Abstract: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.