Abstract: A semiconductor memory device includes a first substrate defining a cell array region, a mold structure including a plurality of gate electrodes sequentially spaced and stacked on the first substrate in a step form, and a channel hole defined as penetrating the plurality of gate electrodes on the cell array region in a vertical direction perpendicular to an upper surface of the first substrate. The device includes an information storage layer along side walls and a bottom surface of the channel hole, the information storage layer including a blocking insulation layer along the side walls and the bottom surface of the channel hole, a charge storage layer on the blocking insulation layer, and a tunneling insulation layer. The device includes a channel layer on the information storage layer inside the channel hole, and an insulation pattern arranged to fill the channel hole on the channel layer.

Abstract: An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

Abstract: An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A pixel array may include an array of microlenses, an array of photodetectors, and an array of color filters. The array of microlenses concentrate incoming light through respective filters in the array of color filters to respective photodetectors in the array of photodetectors. An anti-reflective layer is included between the photodetectors and color filters. The anti-reflective layer includes a first layer having a first index of refraction, a second layer closer to the color filter than the first layer having a second, higher, index of refraction, and a lattice adjusting layer between the first and second layers. The second layer includes a rutile phase TiO2 layer and the lattice adjusting layer includes a crystalline material having a lattice constant similar to that of the rutile phase TiO2 layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.

Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.

Abstract: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate.

Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.

Abstract: A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

Abstract: Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.

Abstract: A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.

Abstract: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate.