Patents by Inventor Gukil AN

Gukil AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220190136
    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.
    Type: Application
    Filed: March 4, 2022
    Publication date: June 16, 2022
    Inventors: Seungseok HA, Gukil AN, Keun Hwi CHO, Sungmin KIM
  • Patent number: 11296204
    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 5, 2022
    Inventors: Seungseok Ha, Gukil An, Keun Hwi Cho, Sungmin Kim
  • Patent number: 10957373
    Abstract: A semiconductor memory device includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines, a voltage generator that supplies a first voltage to the row decoder and supplies a second voltage to the write drivers and sense amplifiers, and a data buffer that is connected to the write drivers and sense amplifiers and transfers data between the write drivers and sense amplifiers and an external device. At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor to amplify a voltage.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun Hwi Cho, Seunghan Park, Hyo-Jin Kim, Gukil An
  • Publication number: 20200013870
    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.
    Type: Application
    Filed: May 21, 2019
    Publication date: January 9, 2020
    Inventors: Seungseok HA, Gukil AN, Keun Hwi CHO, Sungmin KIM
  • Publication number: 20200013446
    Abstract: A semiconductor memory device includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines, a voltage generator that supplies a first voltage to the row decoder and supplies a second voltage to the write drivers and sense amplifiers, and a data buffer that is connected to the write drivers and sense amplifiers and transfers data between the write drivers and sense amplifiers and an external device. At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor to amplify a voltage.
    Type: Application
    Filed: May 31, 2019
    Publication date: January 9, 2020
    Inventors: Keun Hwi CHO, Seunghan PARK, Hyo-Jin KIM, Gukil AN