Abstract: The present invention provides a desktop sterilizer for books. The sterilizer includes an openable main body which has a sterilization chamber therein and is closable by a door so as to be openable through an opening, and a book holder which is provided in the sterilization chamber to maintain the covers of a book in a state of being unfolded. The sterilizer further includes a sterilizing UV lamp which sterilizes the book, and an air discharger which is connected to a blower and blows air towards the proximal edges of pages bound to a book spine of the book held by the book holder, thus opening the pages of the book.

Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Abstract: An image sensor for high-speed data readout is provided. The image sensor includes a line memory block temporarily storing a digital signal in unit of lines which is generated based on an analog signal output from a pixel array. The line memory block includes a plurality of line memories, a plurality of data line pairs respectively connecting the line memories to a sense amplifying unit, and a plurality of data line prechargers each including at least two precharge units separately connected with a corresponding one of the data line pairs to precharge the corresponding data line pair with a predetermined precharge voltage. Accordingly, the image sensor performs high-speed digital signal readout based on precharge operation of the data line prechargers.

Abstract: An analog-to-digital converter (ADC) includes first and second circuits, a differential amplifier, a comparator and a digital-to-analog converter (DAC). The first circuit samples a reset voltage, amplifies the sampled reset voltage, and subtracts a first reference voltage from the amplified reset voltage to produce a first difference. The second circuit samples a signal voltage, amplifies the sampled signal voltage, and subtracts a second reference voltage from the amplified signal voltage to produce a second difference. The differential amplifier produces a third difference based a comparison of the first and second differences from the first and second circuits. The comparator compares an output of the differential amplifier with at least one predetermined comparison voltage and outputs a comparison result as a digital value. The DAC is connected to the first and second circuits and the comparator, and controls the first and second reference voltages in response to the digital value.

Abstract: The invention is directed generally to a correlated double-sampling (CDS) circuit using a smaller number of capacitors than conventional circuits. In embodiments of the invention, a first portion of the CDS circuit uses just two capacitors to sample the reset voltage, amplify the sampled reset voltage, and subtract a first reference voltage from the amplified reset voltage. A second portion of the CDS circuit uses just two capacitors to sample the signal voltage, amplify the sampled signal voltage, and subtract a second reference voltage from the amplified signal voltage. Embodiments of the invention also provide a cyclic analog-to-digital converter (ADC) including the CDS circuit.

Abstract: A method for operating an image capture device having a sensor with an array of first and second pixels includes capturing an image a plurality of times with the second pixels to produce a corresponding second image signal, the second pixels being white pixels, capturing the image a single time with the first pixels to produce a corresponding first image signal, inputting selecting signals to the sensor via a row driver to obtain the first and second image signals from the first and second pixels, respectively, and converting the first and second image signals to respective digital values via an analog-to-digital converter.

Abstract: Provided is a pixel circuit in a CMOS image sensor, a structure thereof, and a method of operating the same. The pixel includes: a photodiode; a floating diffusion node connected to the photodiode through a first switch; a source follower responsive to a voltage of the floating diffusion node. The voltage of the floating diffusion node is applied to the source follower through capacitance coupling.

Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor includes a photodiode, a switch and a comparator. The switch transfers a sensing signal to a sensing node from the photodiode. The comparator, which is directly connected to the sensing node, compares the sensing signal of the sensing node with a reference signal. The comparator outputs a signal corresponding to a voltage difference between the sensing signal and the reference signal.

Abstract: Example embodiments relate to a pixel structure of a CMOS image sensor, and associated methods. The pixel structure may include a substrate of a first-conductivity, a photodiode region of a second conductivity in the first-conductivity substrate, and a capacitor electrode on the second-conductivity photodiode region.

Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Abstract: A time-interleaved bandpass delta-sigma modulator is developed which includes a first adder and a second adder and a comparator. An input signal is transmitted to the first adder according to the clock frequency of each channel block, and an n channel block output un of the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output vn of the second adder is transmitted to the second adder of an n+2 block, and an output yn that passes through an n block comparator is transmitted to the first adder and the second adder of an n+2 block. Therefore, a modulator sequentially receives output from the comparator of each block for generating the final output y.

Abstract: A time-interleaved bandpass delta-sigma modulator is developed which includes a first adder and a second adder and a comparator. An input signal is transmitted to the first adder according to the clock frequency of each channel block, and an n channel block output un of the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output vn of the second adder is transmitted to the second adder of an n+2 block, and an output yn that passes through an n block comparator is transmitted to the first adder and the second adder of an n+2 block. Therefore, a modulator sequentially receives output from the comparator of each block for generating the final output y.

Abstract: Disclosed is a multiple access method for sharing pseudo-noise code by time division transmission in wireless telemetry system, which transmits same time information from a CU (Control Unit) to all RT (Remote Terminal), and each RT transmits data by time division using the time information provided by the CU. Also, each RT decides the respective transmission time using the time information provided by the CU. After each RT transmits data by time division, if the transmitted data has an error, each RT transmits data by time division in repsonse to the retransmission request of the CU.

Abstract: A burst mode receiving apparatus having an offset compensating function and a data recovery method thereof, including an intermediate value detector to detect and output an intermediate value of an input signal input from an outside source in response to a switching control signal; an amplifier to amplify and output a difference between the input signal and a reference value; an offset compensator to generate a compensation signal having a level varied corresponding to the amplified result input from the amplifier and a compensation control signal; a summing portion to add the compensation signal and the intermediate value to output the added result as the reference value to the amplifier; and a controller to generate the switching control signal and the compensation control signal corresponding to a result obtained by analyzing the amplified result input from the amplifier and a reset signal input from the outside source.

Abstract: A burst mode receiving apparatus having an offset compensating function and a data recovery method thereof, including an intermediate value detector to detect and output an intermediate value of an input signal input from an outside source in response to a switching control signal; an amplifier to amplify and output a difference between the input signal and a reference value; an offset compensator to generate a compensation signal having a level varied corresponding to the amplified result input from the amplifier and a compensation control signal; a summing portion to add the compensation signal and the intermediate value to output the added result as the reference value to the amplifier; and a controller to generate the switching control signal and the compensation control signal corresponding to a result obtained by analyzing the amplified result input from the amplifier and a reset signal input from the outside source.