Abstract: Provided is a semiconductor package. The semiconductor package may include a first redistribution structure, a first semiconductor chip including a first surface and a second surface, the first surface being disposed to face the first redistribution structure, a second redistribution structure disposed on the second surface of the first semiconductor chip and including a second insulating layer and a second redistribution layer, a first sealing layer disposed between the first and second redistribution structures and configured to cover the second surface of the first semiconductor chip, and a connection structure configured to connect the first and the second redistribution structures, wherein the second redistribution layer includes a first via and a second via on the first via, wherein the first via includes first and second seed layers, and a conductive layer on the second seed layer, and wherein the first sealing layer includes a photosensitive insulating material.

Abstract: A semiconductor package including a first redistribution structure including a first redistribution layer disposed therein, a first semiconductor chip disposed on the first redistribution structure, an insulating layer surrounding a sidewall of the first semiconductor chip, the insulating layer spaced apart from the first semiconductor chip in a horizontal direction, a first connection structure extending through the insulating layer in a vertical direction, connected to the first redistribution structure, and includes a first via disposed inside the insulating layer. A second connection structure disposed between the first semiconductor chip and the first connection structure, extends through the insulating layer in the vertical direction, connected to the first redistribution structure, and includes a second via disposed inside the insulating layer. A molding layer covering the first semiconductor chip, a sidewall and an upper surface of the insulating layer.

Abstract: A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantiall

Abstract: A method of manufacturing a semiconductor package includes forming an insulating layer; forming a seed layer on the insulating layer; forming a photoresist layer on the seed layer; forming a plurality of line pattern holes by patterning the photoresist layer, a horizontal length of a middle portion of each of the plurality of line pattern holes being less than a horizontal length of an upper portion of each of the plurality of line pattern holes and a horizontal length of a lower portion of each of the plurality of line pattern holes; and forming a redistribution line pattern by performing a plating process using a portion of the seed layer exposed by the plurality of line pattern holes.

Abstract: A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantiall

Abstract: A method of manufacturing a semiconductor package includes forming an insulating layer; forming a seed layer on the insulating layer; forming a photoresist layer on the seed layer; forming a plurality of line pattern holes by patterning the photoresist layer, a horizontal length of a middle portion of each of the plurality of line pattern holes being less than a horizontal length of an upper portion of each of the plurality of line pattern holes and a horizontal length of a lower portion of each of the plurality of line pattern holes; and forming a redistribution line pattern by performing a plating process using a portion of the seed layer exposed by the plurality of line pattern holes.

Abstract: A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

Abstract: A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

Abstract: A method of manufacturing a semiconductor package includes adding an insulating frame to a surface of a carrier substrate, wherein the insulating frame covers a side surface of a first metal layer on the surface of the carrier substrate and bringing a cover insulating layer into contact with the insulating frame and the first metal layer, wherein the cover insulating layer covers at least one semiconductor chip.

Abstract: A method of manufacturing a semiconductor package includes applying a cutter to a boundary between a main portion of a second metal layer and an edge portion of the second metal layer that surrounds the main portion, the second metal layer being on an upper surface of a first metal layer disposed on an upper surface of a carrier substrate, peeling the edge portion of the second metal layer from the first metal layer, forming a cover insulating layer on an upper surface of the main portion of the second metal layer, and disposing a semiconductor chip on an upper surface of the cover insulating layer.

Abstract: In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.

Abstract: A semiconductor package including a first redistribution structure including a first redistribution layer disposed therein, a first semiconductor chip disposed on the first redistribution structure, an insulating layer surrounding a sidewall of the first semiconductor chip, the insulating layer spaced apart from the first semiconductor chip in a horizontal direction, a first connection structure extending through the insulating layer in a vertical direction, connected to the first redistribution structure, and includes a first via disposed inside the insulating layer. A second connection structure disposed between the first semiconductor chip and the first connection structure, extends through the insulating layer in the vertical direction, connected to the first redistribution structure, and includes a second via disposed inside the insulating layer. A molding layer covering the first semiconductor chip, a sidewall and an upper surface of the insulating layer.

Abstract: Provided is a semiconductor package. The semiconductor package may include a first redistribution structure, a first semiconductor chip including a first surface and a second surface, the first surface being disposed to face the first redistribution structure, a second redistribution structure disposed on the second surface of the first semiconductor chip and including a second insulating layer and a second redistribution layer, a first sealing layer disposed between the first and second redistribution structures and configured to cover the second surface of the first semiconductor chip, and a connection structure configured to connect the first and the second redistribution structures, wherein the second redistribution layer includes a first via and a second via on the first via, wherein the first via includes first and second seed layers, and a conductive layer on the second seed layer, and wherein the first sealing layer includes a photosensitive insulating material.

Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

Abstract: A power module is disclosed. A power module according to an embodiment of the present disclosure may include a first substrate and a second substrate spaced apart from each other, an electronic device unit provided on at least either one of the first and second substrates, and a lead frame unit provided between the first and second substrates. One side of the lead frame unit may be connected to an external circuit, and the other side thereof may be configured to electrically connect the first and second substrates. Accordingly, the lead frame unit may perform a function of electrically connecting the first and second substrates instead of a via spacer in the related art.

Abstract: A power module according implementations of the present disclosure includes a bonding layer for bonding two adjacent members. The bonding layer is formed by melting, applying, and solidifying a bonding material that has excellent thermal conductivity and electrical conductivity. The melted bonding material includes a plurality of anti-tilting members. The two members bonded during the process of solidifying the melted bonding material are supported by the plurality of anti-tilting members. This may allow tilting caused during the formation of the bonding layer to be suppressed.

Abstract: A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantiall

Abstract: A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

Abstract: A method of manufacturing a semiconductor package includes forming an insulating layer; forming a seed layer on the insulating layer; forming a photoresist layer on the seed layer; forming a plurality of line pattern holes by patterning the photoresist layer, a horizontal length of a middle portion of each of the plurality of line pattern holes being less than a horizontal length of an upper portion of each of the plurality of line pattern holes and a horizontal length of a lower portion of each of the plurality of line pattern holes; and forming a redistribution line pattern by performing a plating process using a portion of the seed layer exposed by the plurality of line pattern holes.

Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.