Abstract: The invention relates to method and system for feature extraction from an input image from a plurality of images in an image sensor pipeline. The method includes determining a number of logical convolutional operations to be performed, within a reconfigurable convolutional cluster engine, based on a size of an input feature map corresponding to the input image; performing a set of concurrent row wise convolutions on the input feature map, based on the number of logical convolutional operations; performing at least one of a maximum pooling or an average pooling operation on the set of corresponding convolution output through one or more pooling elements to generate a set of pooling output; and generating an output feature map based on the set of pooling output.

Abstract: Disclosed is a reconfigurable parallel 3-Dimensional (3-D) convolution engine for performing 3-D Convolution and parallel feature map extraction on an image. The reconfigurable parallel 3-D convolution engine further comprises a plurality of CNN reconfigurable engines configured to perform 3-D convolution, in parallel, to process a plurality of feature maps, a kernel memory space, present in each instance of CNN reconfigurable engine, capable for holding a set of parameters associated to a network layer having each operational instance of CNN reconfigurable engine, and at least one memory controller, an Input Feature Map Memory (FMM) cluster and an Output FMM cluster.

Abstract: Disclosed is a convolution operator system comprising a Convolution Neural Network (CNN) reconfigurable engine including a plurality of Mini Parallel Rolling Engines (MPREs) for performing a convolution operation concurrently on an image. An input router receives image data. A controller allocates image data to computing blocks through a set of data flow control blocks. Each computing block produces a convolution output corresponding to each row of the image. The controller allocates a plurality of group having one or more computing blocks to generate a set of convolution output. Further, a pipeline adder aggregates the set of convolution output to produce an aggregated convolution output. An output router transmits either the convolution output or the aggregated convolution output for performing subsequent convolution operation to generate a convolution result for the image data.

Abstract: A method for generating a simulation timeline encoded packets view is disclosed. In some embodiments, the method includes receiving a type string from each of a plurality of simulation testbench components. The method further includes assigning a unique type code to each of the plurality of simulation testbench components based on the type string. The method further includes iteratively receiving from at least one of the plurality of simulation testbench components, a plurality of data strings along with the corresponding assigned unique type code. The method further includes storing each of the plurality of data strings marked with an associated receipt timestamp. The method further includes contemporaneously generating at each iteration, a simulation timeline encoded packets view for each of the plurality of simulation testbench components. The method further includes contemporaneously rendering at each iteration the simulation timeline encoded packets view via a Graphical User Interface (GUI).

Abstract: Disclosed is a convolution operator system for performing a convolution operation concurrently on an image. An input router receives image data. A controller allocates image data to a set of computing blocks based on the size of the image data and number of available computing blocks. Each computing block produces a convolution output corresponding to each row of the image. The controller allocates a plurality of group having one or more computing blocks to generate a set of convolution output. Further, a pipeline adder aggregates the set of convolution output to produce an aggregated convolution output. An output router transmits either the convolution output or the aggregated convolution output for performing subsequent convolution operation to generate a convolution result for the image data.

Abstract: A Convolution Multiply and Accumulate-Xtended (CMAC-X) system (102) for performing a convolution operation with functional safety mechanism is disclosed. The CMAC-X system (102) receives image data pertaining to an image. The image data comprises a set of feature matrix, a kernel size and depth information. Further, the CMAC-X system (102) generates a convoluted data based on convolution operation for each feature matrix, The CMAC-X system (102) performs an accumulation of the convoluted data to generate accumulated data, when the convolution operation for each feature matrix is performed. The CMAC-X system (102) further performs an addition of a predefined value to the accumulated data to generate added data. Further, the CMAC-X system (102) filters the added data. Further, the CMAC-X system (102) comprises a functional safety unit to verify a functionality of the CMAC-X system (102), thereby performing the convolution operation of the image with functional safety mechanism.

Abstract: A Convolution Multiply and Accumulate (CMAC) system for performing a convolution operation is disclosed. The CMAC system receives image data pertaining to an image. The image data comprises a set of feature matrix, a kernel size and depth information. Further, the CMAC system generates a convoluted data based on convolution operation for each feature matrix. The CMAC system performs an accumulation of the convoluted data to generate accumulated data, when the convolution operation for each feature matrix is performed. The CMAC system further performs an addition of a predefined value to the accumulated data to generate added data. Further, the CMAC system filters the added data to provide a convolution result for the image, thereby performing the convolution operation of the image.

Abstract: Disclosed is a reconfigurable convolution engine for performing a convolution operation on an image. A data receiving module receives image data. A determination module determines a kernel size based on the image data, clock speed associated to the convolution engine and number of available on-chip resources. An allocation module allocates a plurality of instances based on the kernel size. Each instance of the plurality of instances further comprises a set of computing blocks operating concurrently. Each computing block is configured to perform convolution operation on the feature map of the image. An aggregation module aggregates the convolution output of each computing block for each instance of the plurality of instances to produce a convolution result for the image.

Abstract: Disclosed is a reconfigurable parallel 3-Dimensional (3-D) convolution engine for performing 3-D Convolution and parallel feature map extraction on an image. The reconfigurable parallel 3-D convolution engine further comprises a plurality of CNN reconfigurable engines configured to perform 3-D convolution, in parallel, to process a plurality of feature maps, a kernel memory space, present in each instance of CNN reconfigurable engine, capable for holding a set of parameters associated to a network layer having each operational instance of CNN reconfigurable engine, and at least one memory controller, an Input Feature Map Memory (FMM) cluster and an Output FMM cluster.

Abstract: A Convolution Multiply and Accumulate-Xtended (CMAC-X) system (102) for performing a convolution operation with functional safety mechanism is disclosed. The CMAC-X system (102) receives image data pertaining to an image. The image data comprises a set of feature matrix, a kernel size and depth information. Further, the CMAC-X system (102) generates a convoluted data based on convolution operation for each feature matrix, The CMAC-X system (102) performs an accumulation of the convoluted data to generate accumulated data, when the convolution operation for each feature matrix is performed. The CMAC-X system (102) further performs an addition of a predefined value to the accumulated data to generate added data. Further, the CMAC-X system (102) filters the added data. Further, the CMAC-X system (102) comprises a functional safety unit to verify a functionality of the CMAC-X system (102), thereby performing the convolution operation of the image with functional safety mechanism.

Abstract: Disclosed is a convolution operator system comprising a Convolution Neural Network (CNN) reconfigurable engine including a plurality of Mini Parallel Rolling Engines (MPREs) for performing a convolution operation concurrently on an image. An input router receives image data. A controller allocates image data to computing blocks through a set of data flow control blocks. Each computing block produces a convolution output corresponding to each row of the image. The controller allocates a plurality of group having one or more computing blocks to generate a set of convolution output. Further, a pipeline adder aggregates the set of convolution output to produce an aggregated convolution output. An output router transmits either the convolution output or the aggregated convolution output for performing subsequent convolution operation to generate a convolution result for the image data.

Abstract: A Convolution Multiply and Accumulate (CMAC) system for performing a convolution operation is disclosed. The CMAC system receives image data pertaining to an image. The image data comprises a set of feature matrix, a kernel size and depth information. Further, the CMAC system generates a convoluted data based on convolution operation for each feature matrix. The CMAC system performs an accumulation of the convoluted data to generate accumulated data, when the convolution operation for each feature matrix is performed. The CMAC system further performs an addition of a predefined value to the accumulated data to generate added data. Further, the CMAC system filters the added data to provide a convolution result for the image, thereby performing the convolution operation of the image.

Abstract: Disclosed is a convolution operator system for performing a convolution operation concurrently on an image. An input router receives image data. A controller allocates image data to a set of computing blocks based on the size of the image data and number of available computing blocks. Each computing block produces a convolution output corresponding to each row of the image. The controller allocates a plurality of group having one or more computing blocks to generate a set of convolution output. Further, a pipeline adder aggregates the set of convolution output to produce an aggregated convolution output. An output router transmits either the convolution output or the aggregated convolution output for performing subsequent convolution operation to generate a convolution result for the image data.

Abstract: Disclosed is a reconfigurable convolution engine for performing a convolution operation on an image. A data receiving module receives image data. A determination module determines a kernel size based on the image data, clock speed associated to the convolution engine and number of available on-chip resources. An allocation module allocates a plurality of instances based on the kernel size. Each instance of the plurality of instances further comprises a set of computing blocks operating concurrently. Each computing block is configured to perform convolution operation on the feature map of the image. An aggregation module aggregates the convolution output of each computing block for each instance of the plurality of instances to produce a convolution result for the image.

Abstract: A reconfigurable convolution engine for performing a convolution operation on an image is disclosed. A data receiving module receives image data. A determination module determines a kernel size based on the image data, clock speed associated to the convolution engine and available on-chip resources. A generation module generates a plurality of instances based on the kernel size. A configuration module configures an adder engine comprising a plurality of adders configured to operate in a pipelined structure and in parallel with the plurality of instances. An execution module executes the convolution operation on each of the plurality of instances and the adder engine. A filtering module filters an output of the convolution operation by using a filter function configured to operate on a predefined threshold function.

Abstract: A reconfigurable convolution engine for performing a convolution operation on an image is disclosed. A data receiving module receives image data. A determination module determines a kernel size based on the image data, clock speed associated to the convolution engine and available on-chip resources. A generation module generates a plurality of instances based on the kernel size. A configuration module configures an adder engine comprising a plurality of adders configured to operate in a pipelined structure and in parallel with the plurality of instances. An execution module executes the convolution operation on each of the plurality of instances and the adder engine. A filtering module filters an output of the convolution operation by using a filter function configured to operate on a predefined threshold function.