Abstract: A synchronization pattern detector is disclosed. The synchronization pattern detector includes a plurality of cost function engines which each calculate a partial cost of a subset of the incoming data bits. The cost function engines are arranged in a two dimensional array where each row processes data samples associated with a particular phase of the incoming data bits. These partial costs are summed together to calculate a total cost for a particular symbol stream. Summing circuits are configured to calculate costs for various scenarios, such as transmit baudrate equal to the receiver baudrate; transmit baudrate slower than the receiver baudrate; and transmit baudrate faster than the receiver baudrate. In addition to detecting the synchronization pattern, the detector may also provide information that is used to adjust parameters of the read circuit to better align the receiver baudrate to the transmit baudrate.

Abstract: A synchronization pattern detector is disclosed. The synchronization pattern detector includes a plurality of pattern detectors, which may be correlators or cost function engines which each calculate a partial metric, which may be a correlation score or cost value of a subset of the incoming data bits, respectively. The pattern detectors are arranged in a two dimensional array where each row processes data samples associated with a particular phase of the incoming data bits. These partial metrics are summed together to calculate a total metric for a particular symbol stream. Summing circuits are configured to calculate metrics for various scenarios, such as transmit baudrate equal to, slower than, or faster than the receiver baudrate. In addition to detecting the synchronization pattern, the detector may also provide information that is used to adjust parameters of the read circuit to better align the receiver baudrate to the transmit baudrate.

Abstract: A technique for reducing or eliminating effects of frequency and phase offset in a communications system includes implementing a demodulator having a Kalman filter based phase-locked loop for phase-shift keying or quadrature amplitude modulated signals. In an acquisition mode of operation, the Kalman filter based phase-locked loop continuously updates an error correction signal until an error between a received version of a predetermined signal transmitted using phase-shift keying or quadrature amplitude modulation and the predetermined signal is at or near zero. In a tracking mode of operation, the Kalman filter based phase-locked loop adjusts the error correction signal to maintain the error between the received signal and a predicted signal at or near zero.

Abstract: A wireless communications device includes a receiver having a phase detector configured to extract frequency offset and provide a corresponding error signal generated based on a baseband version of a received radio frequency signal and an expected transmitted data signal. The receiver has a phase-locked loop configured to generate an error correction signal based on a phase of the error signal and a predicted instantaneous phase of the error signal. The receiver has a correction circuit configured to provide a corrected baseband version of the received radio frequency signal based on the baseband version of the received radio frequency signal and the error correction signal. The receiver may have a re-encoding-based processing circuit configured to provide the expected transmitted data signal based on a preliminarily decoded symbol.

Abstract: A system and method to improve the accuracy of the measurement of round trip delay in a high accuracy distance measurement (HADM) is disclosed. In one embodiment, the traditional parabolic estimation is used. However, an estimation error is used to compensate for the inaccuracy of the parabolic estimation. This correction may reduce the standard deviation of a measurement by 50% or more. In another embodiment, the parabolic estimation is not used; rather, a different estimation is used, such as an absolute value estimation. In some tests, the absolute value estimation improved the mean measurement value and reduced the standard deviation by 50%.

Abstract: A system that is capable of detecting a Man in the Middle attack is disclosed. The system includes a receive circuit for receiving incoming packets. The system also includes a digitized model of at least part of the receive circuit and optionally part of the transmit circuit. The system compares the output from the digitized model with the output from the read circuit to determine the likelihood of a Man in the Middle Attack. In certain embodiments, the digitized model is a finite impulse response filter with multiple taps. The system correctly identifies Man in the Middle attacks more than 90% of the time when the signal to noise ratio is greater than 20 dB.

Abstract: A system and method to improve the accuracy of the measurement of round trip delay in a high accuracy distance measurement (HADM) is disclosed. In one embodiment, the traditional parabolic estimation is used. However, an estimation error is used to compensate for the inaccuracy of the parabolic estimation. This correction may reduce the standard deviation of a measurement by 50% or more. In another embodiment, the parabolic estimation is not used; rather, a different estimation is used, such as an absolute value estimation. In some tests, the absolute value estimation improved the mean measurement value and reduced the standard deviation by 50%.

Abstract: A system that is capable of detecting a Man in the Middle attack is disclosed. The system includes a receive circuit for receiving incoming packets. The system also includes a digitized model of at least part of the receive circuit and optionally part of the transmit circuit. The system compares the output from the digitized model with the output from the read circuit to determine the likelihood of a Man in the Middle Attack. In certain embodiments, the digitized model is a finite impulse response filter with multiple taps. The system correctly identifies Man in the Middle attacks more than 90% of the time when the signal to noise ratio is greater than 20 dB.

Abstract: A system that is capable of detecting a Man in the Middle attack is disclosed. The system includes a receive circuit for receiving incoming packets. The system also includes a digitized model of at least part of the receive circuit and optionally part of the transmit circuit. The system compares the output from the digitized model with the output from the read circuit to determine the likelihood of a Man in the Middle Attack. In certain embodiments, the digitized model is a finite impulse response filter with multiple taps. The system correctly identifies Man in the Middle attacks more than 90% of the time when the signal to noise ratio is greater than 20 dB.

Abstract: In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.

Abstract: A system that includes a Viterbi Equalizer having adaptive signal levels is disclosed. Each branch metric of the Viterbi Equalizer compares the value of the incoming bit to one of a plurality of different expected signal levels. A set of default signal values may be used by the Viterbi Equalizer. The system is also configured to determine whether these default expected signal levels are acceptable by monitoring the incoming data bits. If it is determined that the actual signal levels of the incoming data bits differ from the default expected signal levels by more than a predetermined amount, the signal levels used by the Viterbi Equalizer may be changed from default signal levels to the adaptive signal levels. The adaptive signal levels may be determined using the synchronization pattern.

Abstract: A wireless device may include: a radio frequency (RF) front end circuit to receive and process an RF signal; a mixer to downconvert the RF signal to a second frequency signal; a digitizer to digitize the second frequency signal; a channel filter to channel filter the digitized signal; a selection circuit having a first input coupled to the channel filter and a plurality of outputs each to couple to one of a plurality of demodulators; and the plurality of demodulators coupled to the selection circuit. The selection circuit may route the channel filtered digitized signal to a first demodulator of the plurality of demodulators based on a first configuration setting. The wireless device may also include a non-volatile storage with a configuration file including the first configuration setting. The configuration file may be automatically generated by a hardware configurator in response to a plurality of user input parameters.

Abstract: A system and method for detecting the presence of a Bluetooth or Zigbee signal within a short period of time is disclosed. The signal identification circuit has two stages, a first stage that processes windows to determine whether noise is present, and a second stage that processes long windows to determine whether the signal is a particular lower-power network protocol. The signal identification circuit can be configured to detect Bluetooth at 1 Mbps, Bluetooth at 2 Mbps or Zigbee. The signal identification signal may be used to allow a lower-power network controller to coexist with a high duty cycle WiFi controller. The signal identification circuit may also be used for other functions, such as powering on a lower-power network controller, determining CCA, or determining which channel a packet is being transmitted on.

Abstract: An apparatus comprises an RF receiver for receiving an RF signal. The RF receiver includes front-end circuitry to generate a first down-converted signal, and a plurality of signal detectors to generate a corresponding plurality of detection signals from signals derived from the down-converted signal. The RF receiver further includes a controller to provide at least one control signal to the front-end circuitry based on the plurality of detection signals.

Abstract: In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.

Abstract: A system and method for detecting the presence of a Bluetooth or Zigbee signal within a short period of time is disclosed. The signal identification circuit has two stages, a first stage that processes windows to determine whether noise is present, and a second stage that processes long windows to determine whether the signal is a particular lower-power network protocol. The signal identification circuit can be configured to detect Bluetooth at 1 Mbps, Bluetooth at 2 Mbps or Zigbee. The signal identification signal may be used to allow a lower-power network controller to coexist with a high duty cycle WiFi controller. The signal identification circuit may also be used for other functions, such as powering on a lower-power network controller, determining CCA, or determining which channel a packet is being transmitted on.

Abstract: A Viterbi Equalizer having a limited number of stages is disclosed. In some embodiments, the Viterbi Equalizer may have only four stages. The Viterbi Equalizer produces soft decisions, which comprise a final decision and reliability information related to that final decision. The Viterbi Equalizer is able to provide reliability information even if all paths do not converge on the final decision at the last stage. The reliability information is calculated based on if and when the paths in the trellis converge on a final decision. This reliability information can be used downstream, such as by another Viterbi Algorithm block to perform forward error correction. The use of soft decision provides gains of up to several dB in performance. Additionally, the Viterbi Equalizer is low cost and readily implemented in hardware or software.

Abstract: A system and method for detecting the presence of a Bluetooth or Zigbee signal within a short period of time is disclosed. The signal identification circuit has two stages, a first stage that processes windows to determine whether noise is present, and a second stage that processes long windows to determine whether the signal is a particular lower-power network protocol. The signal identification circuit can be configured to detect Bluetooth at 1 Mbps, Bluetooth at 2 Mbps or Zigbee. The signal identification signal may be used to allow a lower-power network controller to coexist with a high duty cycle WiFi controller. The signal identification circuit may also be used for other functions, such as powering on a lower-power network controller, determining CCA, or determining which channel a packet is being transmitted on.

Abstract: A system and method for detecting and receiving packets that are transmitted over a network that utilizes a plurality of channels is disclosed. The system includes a radio circuit, which can be configured to receive packets over a plurality of channels, a processing unit, and a memory in communication with the processing unit. The processing unit loads a set of operating parameters in the radio circuit, which enables the radio circuit to detect and receive packets on a particular channel. If a preamble is not detected within a predetermined time period, the system hops to a different channel by loading a second set of operating parameters in the radio circuit. This process can be repeated for an arbitrary number of channels.

Abstract: A wireless device may include: a radio frequency (RF) front end circuit to receive and process an RF signal; a mixer to downconvert the RF signal to a second frequency signal; a digitizer to digitize the second frequency signal; a channel filter to channel filter the digitized signal; a selection circuit having a first input coupled to the channel filter and a plurality of outputs each to couple to one of a plurality of demodulators; and the plurality of demodulators coupled to the selection circuit. The selection circuit may route the channel filtered digitized signal to a first demodulator of the plurality of demodulators based on a first configuration setting. The wireless device may also include a non-volatile storage with a configuration file including the first configuration setting. The configuration file may be automatically generated by a hardware configurator in response to a plurality of user input parameters.