Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

Abstract: AR glasses includes one or more processors, and at least one of the one or more processors performs: receiving processing of receiving collision prediction information including location information about a dangerous area where a user is predicted to collide with a mobile object and information regarding a trajectory of the mobile object, from an external apparatus; determining processing of deriving a distance between the dangerous area and the user on the basis of the collision prediction information, to determine a danger level corresponding to the distance; generating processing of generating content that prompts danger avoidance depending on the danger level; and display control processing of displaying the content on a display.

Abstract: A semiconductor memory device includes a receiving circuit, a multiplexing circuit, a decoding circuit and a memory cell array. The receiving circuit receives a plurality of input command/address (CA) signals, and generates a plurality of CA signal groups based on the input CA signals and a clock signal. The multiplexing circuit operates in one of a first operation mode and a second operation mode based on a mode selection signal, outputs the plurality of CA signal groups as a plurality of selected CA signal groups in the first operation mode, and generates the plurality of selected CA signal groups by multiplexing the plurality of sub-CA signals included in the plurality of CA signal groups in the second operation mode. The decoding circuit generates a plurality of output CA signals based on the plurality of selected CA signal groups.

Abstract: AR glasses includes one or more processors, and at least one of the one or more processors performs: receiving processing of receiving collision prediction information including location information about a dangerous area where a user is predicted to collide with a mobile object and information regarding a trajectory of the mobile object, from an external apparatus; determining processing of deriving a distance between the dangerous area and the user on the basis of the collision prediction information, to determine a danger level corresponding to the distance; generating processing of generating content that prompts danger avoidance depending on the danger level; and display control processing of displaying the content on a display.

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

Abstract: A semiconductor memory device includes a receiving circuit, a multiplexing circuit, a decoding circuit and a memory cell array. The receiving circuit receives a plurality of input command/address (CA) signals, and generates a plurality of CA signal groups based on the input CA signals and a clock signal. The multiplexing circuit operates in one of a first operation mode and a second operation mode based on a mode selection signal, outputs the plurality of CA signal groups as a plurality of selected CA signal groups in the first operation mode, and generates the plurality of selected CA signal groups by multiplexing the plurality of sub-CA signals included in the plurality of CA signal groups in the second operation mode. The decoding circuit generates a plurality of output CA signals based on the plurality of selected CA signal groups.

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.