Patents by Inventor Gunjan Goel

Gunjan Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9760666
    Abstract: A planned schematic for an electronic system is hierarchically divided into base-level schematic blocks which may be designed individually. In accordance with a plurality of sets of design requirements, variant overlays are designed for each base-level schematic block, each overlay including variant parameter values which may replace corresponding parameter values of the schematic blocks. The schematic blocks are integrated to generate a system-level schematic, and the variant overlays for a given set of design requirements are merged to generate a system variant overlay. Parameter values of the system variant overlay may then replace corresponding parameter values of the system-level schematic to generate a variant schematic for the given set of design requirements.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 12, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shilpa Gandotra, Aditya Chandra, Gunjan Goel, Inderpal Singh, Nikhil Gupta, Ishani Jain