Patents by Inventor Gunjeet D. Baweja

Gunjeet D. Baweja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cache memory architecture with on-chip tag array and off-chip data array
    Patent number: 6247094
    Abstract: The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 12, 2001
    Assignee: Intel Corporation
    Inventors: Harsh Kumar, Gunjeet D. Baweja, Cheng-Feng Chang, Tim W. Chan
  • Cache memory with reduced latency
    Patent number: 6237064
    Abstract: The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: May 22, 2001
    Assignee: Intel Corporation
    Inventors: Harsh Kumar, Gunjeet D. Baweja, Cheng-Feng Chang
  • Method and apparatus for generating a reset signal within an integrated circuit
    Patent number: 5974561
    Abstract: An integrated circuit having a terminal for receiving a first signal, a terminal for receiving a second signal, and circuitry for generating a reset signal is disclosed. The reset signal is asserted based on a transition of the first signal when the second signal is in a predetermined state. In one embodiment the first signal is a suspend clock signal, the second signal is a suspend status signal, and the reset signal is used to reset a resume well within the integrated circuit. Thus, the integrated circuit can be used in a computer system which has a suspend mode with a resume sequence during which the resume well is reset, without requiring that the integrated circuit include an extra terminal for indicating when to reset the resume well.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: October 26, 1999
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Gunjeet D. Baweja, Chin-Shu Tan