Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

Abstract: Efficient hardware architecture for a S1 S-box for a ZUC cipher is described. One circuit includes a first circuit to map an 8-bit input data of a Galois field GF(256) for a 8-bit data path for a ZUC cipher non-linear function component into 4-bit data paths for the ZUC cipher non-linear function component. The circuit further includes other circuits coupled to the first circuit to execute the 4-bit data paths in GF(162) to determine the inverse of the 8-bit input data for the ZUC cipher non-linear function component in GF(162) and to map the inverse in GF(162) to the Galois field GF(256).

Abstract: Efficient hardware architecture for a S1 S-box for a ZUC cipher is described. One circuit includes a first circuit to map an 8-bit input data of a Galois field GF(256) for a 8-bit data path for a ZUC cipher non-linear function component into 4-bit data paths for the ZUC cipher non-linear function component. The circuit further includes other circuits coupled to the first circuit to execute the 4-bit data paths in GF(162) to determine the inverse of the 8-bit input data for the ZUC cipher non-linear function component in GF(162) and to map the inverse in GF(162) to the Galois field GF(256).

Abstract: Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N?=Nrt2f mod M+NL and, subsequently, determining N? mod M.

Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

Abstract: A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.

Abstract: An area efficient multiplier having high performance at modest clock speeds is presented. The performance of the multiplier is based on optimal choice of a number of levels of Karatsuba decomposition. The multiplier may be used to perform efficient modular reduction of large numbers greater than the size of the multiplier.

Abstract: Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.

Abstract: The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1?v2) and multiplying the result (v1?v2) by a constant (c) to produce a second result.

Abstract: A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a respective one of the derived set of polynomials to data output by a preceding one of the set of stages.

Abstract: Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.

Abstract: The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.

Abstract: In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

Abstract: The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1?v2) and multiplying the result (v1?v2) by a constant (c) to produce a second result.

Abstract: The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD.

Abstract: The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a respective one of the derived set of polynomials to data output by a preceding one of the set of stages.