Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Abstract: Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronou

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Abstract: A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides for the conversion of clock signals, commands, and data. The conversion device contains a changeover switch, a delay locked loop and buffer memory for addresses and commands and also for the data, which are driven in a suitable manner by the delay locked loop.

Abstract: An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: An apparatus and a method are proposed, which can be used to delay a deactivation of a row address in the event of repeated access to a bank of an RLDRAM memory module.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: A method and device for measuring voltage of an internal reference voltage source of an integrated semiconductor circuit, in particular, a DRAM, including the steps of comparing a reference voltage to an external comparison voltage with a comparator, forming a measured value for the reference voltage to be set in accordance with a comparison result, switching a commutator by a clock- or software-control to alternatively apply the reference voltage and the comparison voltage to the comparator inputs at the same time, varying one of the reference and comparison voltage to a setpoint voltage value until the comparator output changes its logic value at each commutator switched stage, buffering the voltage values present for each switched state when the logic value changes, forming an average value for the reference voltage from the stored voltage values, and setting the reference voltage as a function of the average value formed.

Abstract: The circuit has a clock input for supplying a first clock signal and a clock generator for generating a second clock signal, said clock generator being phase-locked with respect to the first clock signal. The clock output of the clock generator is connected to a control input of a data transmission unit used for outputting data from the circuit and/or for reading into the circuit essentially in synchronism with the first clock signal. The clock generator has at least two control loops connected in succession which are used for controlling the phase angle of the second clock signal, the first control loop being used to generate from the first clock signal at least two intermediate clock signals, each of which has a particular phase angle with respect to the first clock signal, and the second control loop being used to generate the second clock signal from the intermediate clock signals.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: An apparatus for calibrating the pulse duration of an output signal of a signal source may be used, in particular, for measuring and setting a duty cycle of a signal output from the signal source. The apparatus includes a comparator having a first input, a second input and an output. A reference voltage supply is provided, which is connected to the first input of the comparator. A charge storing capacitor, the charge state of which is adjustable as a function of the pulse duration of the output signal of the signal source, is connected to the second input of the comparator. Finally, the apparatus includes a processor for setting the pulse duration as a function of the comparison signal output at the output of the comparator. The apparatus for signal calibration allows an on-chip calibration and renders complicated external calibration systems superfluous.

Abstract: A test circuit is adapted to test circuits having a high-frequency clock signal. The test circuit is positioned between a conventional tester and the circuit to be tested. The test circuit includes a frequency multiplication circuit which multiplies the clock signal of the conventional tester to produce a high-frequency clock signal. The test circuit also receives control signals from the conventional tester. The control signals are output to the circuit to be tested via a bus.

Abstract: A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.