Abstract: The device is arranged to receive a plurality of separate groups of signals, each group including a given number of redundant digital signals and is to select one of the digital signals from each group for subsequent processing. Memory sections are provided for storing at specific locations in each of the sections the digital signals of the various groups. A clock and counter are used to control an addressing circuit for cycling the addressing of the respective sections and locations such that the digital signals in each group may be successively stored in suitable buffer registers on a time share basis. The redundant signals in each group are then successively released for independent analysis, a preferred or favored digital signal among the redundant signals being selected and stored in a high speed memory section. These stored preferred signals from each of the groups are then available for subsequent processing.