Patents by Inventor Gunnar Nordmark

Gunnar Nordmark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9635145
    Abstract: A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: April 25, 2017
    Assignee: Marvell International Ltd.
    Inventors: Gunnar Nordmark, Kurt Thomas Boden, Lars-Olof Svensson, Par Westlund
  • Patent number: 9525760
    Abstract: A network processing device comprising a plurality of programmable processors coupled together to perform a set of packet processing operations to process a packet received by the network processing device. Ones of the programmable processors being configured to perform a respective subset of the set of packet processing operations with a respective portion of a packet context such that respective programmable processors receives a portion of the packet context, that is less than a full packet context for performing the packet processing operations. The portion of a packet context being dimensioned to perform the respective subset of the packet processing operations.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 20, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Kurt Thomas Boden, Gunnar Nordmark, Mikael Karpberg
  • Patent number: 9178830
    Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: November 3, 2015
    Assignee: Marvell International Ltd.
    Inventors: Gunnar Nordmark, Thomas Bodén, Jakob Carlström, Vitaly Sukonik, Mattias Persson
  • Publication number: 20150163156
    Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Applicant: Marvell International Ltd.
    Inventors: Gunnar NORDMARK, Thomas Bodén, Jakob Carlström, Vitaly Sukonik, Mattias Persson
  • Patent number: 8964594
    Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Marvell International Ltd.
    Inventors: Gunnar Nordmark, Thomas Bodén, Jakob Carlström, Vitaly Sukonik, Mattias Persson
  • Publication number: 20140247835
    Abstract: A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 4, 2014
    Applicant: Marvell International Ltd.
    Inventors: Gunnar Nordmark, Kurt Thomas Boden, Lars-Olof Svensson, Par Westlund
  • Publication number: 20140146827
    Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 29, 2014
    Applicant: Marvell International Ltd.
    Inventors: Gunnar NORDMARK, Thomas BODÉN, Jakob CARLSTRÖM, Vitaly SUKONIK, Mattias PERSSON
  • Patent number: 8725900
    Abstract: The present invention relates to a method and apparatus for pipelined processing of data. When a data packet containing information is received by a processor operating according to pipelined processing, bits are added to the data packet and an intermediate packet, comprising more bits than the received data packet, is generated. To the intermediate packet is associated information reference, the information reference comprising information regarding the length and position of the information in the intermediate packet. As the intermediate packet is processed, changes to the intermediate packet resulting in changes of the length or the position of the information in the intermediate packet will trigger changes of the information reference. When the intermediate packet exits the processor, superfluous bits are removed.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: May 13, 2014
    Assignee: Marvell International Ltd.
    Inventors: Gunnar Nordmark, Thomas Boden, Lars-Olaf Svensson, Par Westlund
  • Patent number: 8630199
    Abstract: A method of and a network processor unit (10) for processing of packets in a network, the network processor (10) comprising: communication interface (14) configured to receive and transmit packets; at least one processing means (16) for processing packets or parts thereof; an embedded switch (12) configured to switch packets between the communication interface (14) and the processing means (16); and wherein the embedded switch (12) is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means (16) for processing thereof, to receive the processed first part of the packet from the processing means (16), and to transmit the processed first part of the packet.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 14, 2014
    Assignee: Marvell International Ltd.
    Inventors: Gunnar Nordmark, Thomas Bodén, Jakob Carlström, Vitaly Sukonik, Mattias Persson
  • Publication number: 20110085464
    Abstract: A method of and a network processor unit (10) for processing of packets in a network, the network processor (10) comprising: communication interface (14) configured to receive and transmit packets; at least one processing means (16) for processing packets or parts thereof; an embedded switch (12) configured to switch packets between the communication interface (14) and the processing means (16); and wherein the embedded switch (12) is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means (16) for processing thereof, to receive the processed first part of the packet from the processing means (16), and to transmit the processed first part of the packet.
    Type: Application
    Filed: May 29, 2009
    Publication date: April 14, 2011
    Inventors: Gunnar Nordmark, Thomas Bodén, Jakob Carlström, Vitaly Sukonik, Mattias Persson
  • Patent number: 7644190
    Abstract: The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronization mechanism adapted to synchronize the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronization mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: January 5, 2010
    Assignee: Xelerated AB
    Inventors: Thomas Stromqvist, Gunnar Nordmark, Lars-Olof Svensson
  • Patent number: 7644256
    Abstract: A method in a processor is presented, in which data is processed in a pipelined manner, the data being included in a plurality of contexts, comprising a first (3), in addition to which a plurality of operations is adapted to be executed on the contexts. The method comprises executing an initial operation step (6a) of a first operation on the first context (3), and subsequently commencing an execution of an initial operation step (7a) of a second operation on the first context before an execution on the first context (3) of a following operation step (6b) of the first operation is completed.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: January 5, 2010
    Assignee: Xelerated AB
    Inventors: Gunnar Nordmark, Thomas Boden
  • Patent number: 7397798
    Abstract: Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the second register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: July 8, 2008
    Assignee: Xelerated AB
    Inventors: Lars-Olov Svensson, Thomas Stromqvist, Gunnar Nordmark, Par Westlund, Joachim Roos
  • Publication number: 20060155771
    Abstract: The present invention relates to a method and apparatus for pipelined processing of data. When a data packet containing information is received by a processor operating according to pipelined processing, bits are added to the data packet and an intermediate packet, comprising more bits than the received data packet, is generated. To the intermediate packet is associated information reference, the information reference comprising information regarding the length and position of the information in the intermediate packet. As the intermediate packet is processed, changes to the intermediate packet resulting in changes of the length or the position of the information in the intermediate packet will trigger changes of the information reference. When the intermediate packet exits the processor, superfluous bits are removed.
    Type: Application
    Filed: April 3, 2003
    Publication date: July 13, 2006
    Inventors: Gunnar Nordmark, Thomas Boden, Lars-Olof Svensson, Par Westlund
  • Publication number: 20060129718
    Abstract: The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronisation mechanism adapted to synchronise the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronisation mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.
    Type: Application
    Filed: July 9, 2003
    Publication date: June 15, 2006
    Inventors: Thomas Stromqvist, Gunnar Nordmark, Lars-Olof Svensson
  • Publication number: 20040215620
    Abstract: Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the first register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.
    Type: Application
    Filed: May 7, 2004
    Publication date: October 28, 2004
    Inventors: Lars-Olov Svensson, Thomas Stromqvist, Gunnar Nordmark, Par Westlund, Joachim Roos