Abstract: A device for managing communication via interfaces in a virtualized system in which a plurality of virtual machines shares a hardware platform which is virtualized with the aid of a hypervisor, and interfaces assigned to the hardware platform access to the interfaces taking place with the aid of a gateway implemented in hardware. A method for operating the device is also described.

Abstract: A method/device for recognizing a microprocessor hardware error, including comparing a first application's first result, running on a first microprocessor, with a second application's second result, running on the first/second microprocessor, with a microcontroller, providing comparison strategies, the hardware error being recognized as a function of the comparison, the microcontroller receiving a first message from the first microprocessor, and receiving a second message from the first microprocessor if the second application runs on the first microprocessor, or receives a first message from the second microprocessor if the second application runs thereon, the first message containing first comparison strategy information and first result information of a first function calculation, the second message containing second comparison strategy information and second result information of a second function calculation, the first and second strategy information being compared, the first and second result informatio

Abstract: A method for securing an application programming interface of a utility program library, including at least one program construct, of a hypervisor, including a configuration of the hypervisor that assigns at least one permissible call of the program construct to at least one guest system of the hypervisor, and a code generation, supported by the configuration, of a declaration of the program construct adapted to the guest system.

Abstract: A method for protecting a working memory, including the following features:—memory areas of the working memory are optionally assigned to a first class or a second class; prior to a program execution, at least the memory areas of the first class are entered into a configuration table of the memory protection unit; and when access to a destination area among the memory areas of the second class is requested during the program execution, the destination area is entered into the configuration table before the access is granted.

Abstract: A hypervisor manages a read buffer, a write buffer and a queuing buffer in a memory used jointly by the first virtual machine and the second virtual machine, the read buffer, the write buffer and the queuing buffer having the same size. The hypervisor assigns the read buffer to a read area readable by the first virtual machine, assigns the write buffer to a write area writable by the second virtual machine and assigns the queuing buffer to a queuing area of the memory that is inaccessible to the first virtual machine and to the second virtual machine. In response to a first request by the first virtual machine, the hypervisor performs a reader-side exchange of the read buffer for the queuing buffer and in response to a second request by the second virtual machine, the hypervisor performs a writer-side exchange of the write buffer for the queuing buffer.

Abstract: A method for the quasi-parallel execution of threads, including: within a time slice, time-limited resources, particularly a computing time, are allotted to the threads by a preemptive first scheduler on the basis of a priority of the threads, and the first scheduler is combined with further schedulers.

Abstract: A method/device for recognizing a microprocessor hardware error, including comparing a first application's first result, running on a first microprocessor, with a second application's second result, running on the first/second microprocessor, with a microcontroller, providing comparison strategies, the hardware error being recognized as a function of the comparison, the microcontroller receiving a first message from the first microprocessor, and receiving a second message from the first microprocessor if the second application runs on the first microprocessor, or receives a first message from the second microprocessor if the second application runs thereon, the first message containing first comparison strategy information and first result information of a first function calculation, the second message containing second comparison strategy information and second result information of a second function calculation, the first and second strategy information being compared, the first and second result informatio

Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.

Abstract: A method for the on-board diagnosis of a control unit which include a hypervisor and at least one guest system operated under the hypervisor. In the method, the guest system receives a diagnosis inquiry at an individual diagnosis address of the guest system from a diagnostic tool with the aid of a communication infrastructure. The guest system makes a self-diagnosis. The guest system receives a hypervisor diagnosis from the hypervisor. The guest system transmits, at its diagnosis address, the self-diagnosis or the hypervisor diagnosis to the diagnostic tool as a function of the diagnosis inquiry.

Abstract: A method for the quasi-parallel execution of threads, including: within a time slice, time-limited resources, particularly a computing time, are allotted to the threads by a preemptive first scheduler on the basis of a priority of the threads, and the first scheduler is combined with further schedulers.

Abstract: A method for monitoring quasi-parallel execution threads in an event-oriented operating system, in which an administration process, privileged by the operating system, monitors operating events triggered by the execution threads with the aid of a kernel of the operating system, and with the aid of the operating events, the administration process constantly monitors a run-time behavior of the execution threads specified by the configuration.

Abstract: A method for the on-board diagnosis of a control unit which include a hypervisor and at least one guest system operated under the hypervisor. In the method, the guest system receives a diagnosis inquiry at an individual diagnosis address of the guest system from a diagnostic tool with the aid of a communication infrastructure. The guest system makes a self-diagnosis. The guest system receives a hypervisor diagnosis from the hypervisor. The guest system transmits, at its diagnosis address, the self-diagnosis or the hypervisor diagnosis to the diagnostic tool as a function of the diagnosis inquiry.

Abstract: A method for updating a virtual machine operated under a hypervisor on a physical machine having a random-access memory and a read-only memory. The hypervisor operates the virtual machine under an individual diagnostic address, the read-only memory storing a machine code of the hypervisor and of the virtual machine. The virtual machine receives an updating request from an external unit under the diagnostic address with the aid of a communication infrastructure and communicates the updating request to the hypervisor, The hypervisor transfers the machine code from the read-only memory into the random-access memory. The hypervisor starts the virtual machine and executes a boot manager of the virtual machine. The boot manager receives a current machine code under the diagnostic address of the virtual machine and exchanges the machine code in the read-only memory at least partially for the current machine code, and the boot manager restarts the virtual machine.

Abstract: A method for operating changing guest systems under a hypervisor, including, on a host system, the hypervisor monitors at least one virtual machine including a guest system. The guest system provides a prompt to the hypervisor, as a function of a system context of the host system, to switch the virtual machine from a first guest system variant to a second guest system variant. The host system carries out the switch in response to the prompt by the guest system.

Abstract: A hypervisor manages a read buffer, a write buffer and a queuing buffer in a memory used jointly by the first virtual machine and the second virtual machine, the read buffer, the write buffer and the queuing buffer having the same size. The hypervisor assigns the read buffer to a read area readable by the first virtual machine, assigns the write buffer to a write area writable by the second virtual machine and assigns the queuing buffer to a queuing area of the memory that is inaccessible to the first virtual machine and to the second virtual machine. In response to a first request by the first virtual machine, the hypervisor performs a reader-side exchange of the read buffer for the queuing buffer and in response to a second request by the second virtual machine, the hypervisor performs a writer-side exchange of the write buffer for the queuing buffer.

Abstract: A method for securing an application programming interface of a utility program library, including at least one program construct, of a hypervisor, including a configuration of the hypervisor that assigns at least one permissible call of the program construct to at least one guest system of the hypervisor, and a code generation, supported by the configuration, of a declaration of the program construct adapted to the guest system.

Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.

Abstract: A method for setting up an array of technical units and such an array are presented. The method is used for the independent setup and operation of an array of technical units, the technical units being connected to one another via a system communication bus, a query for a system resource being transmitted from a querying unit to all other units, all other units checking whether the resource has already been assigned to this unit itself, and all querying units transmitting an appropriate response to the querying units and the system resource being assigned thereto if it is not already assigned to one of the other units.

Abstract: A method and a system are provided for simulating a technical system by means of a model. In the method, at least one simulation tool is stored in an application node, and the model, which is executed under real-time conditions, is stored in a simulation node, using one platform.

Abstract: A method for setting up an array of technical units and such an array are presented. The method is used for the independent setup and operation of an array of technical units, the technical units being connected to one another via a system communication bus, a query for a system resource being transmitted from a querying unit to all other units, all other units checking whether the resource has already been assigned to this unit itself, and all querying units transmitting an appropriate response to the querying units and the system resource being assigned thereto if it is not already assigned to one of the other units.