Abstract: A circuit arrangement for storing a speech signal in a digital speech memory (SP) and reproducing the stored signal comprises among other things a control circuit (SS). The control circuit produces control commands and clock signals for the individual modules of the arrangement. The speech signal to be stored is available in one of various predetermined codes. In order to enable storing speech signals of considerable lengths, it is provided to write the speech signal into the digital speech memory (SS) in a preferred digital code. For this purpose, input converters (EW1, EW2, EW3, EW4) are used which convert the code of the speech signal to be stored from the one it has into the preferred digital code, if the signal is not already available in this code. Multiplexing means (M1, M2), controlled by the control circuit (SS), further convey the converted speech signal to the input of the digital speech memory (SP).